K4Y50164UC Datasheet, PDF (39/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
Figure 26 : Refresh Low (REFL) Row Register
76543210
R[7:0]
Refresh Low Row Register
SADR[7:0]: 00001011₂
Read/write register
REFL[7:0] resets to 00000000₂
R[7:0] - Refresh row field.
This field contains the low-order bits of the row address that will
be refreshed during the next refresh interval. This row address
will be incremented after a REFI command for auto-refresh, or
when the BANK[2:0] field for the REFB register equals the max-
imum bank address for self-refresh.
Figure 27 : IO Configuration (IOCFG) Register
76543210
reserved
ODF[1:0]
IO Configuration Register
SADR[7:0]: 00001111₂
Read/write register
IOCFG[7:0] resets to 00000000₂
ODF[1:0] - Overdrive Function field.
00 - Nominal V_OSW,DQ range
01 - reserved
10 - reserved
11 - reserved
Figure 28 : Current Calibration 0 (CC0) Register
76543210
reserved
CCVALUE0[5:0]
Current Calibration 0 Register
Read/write register
SADR[7:0]: 00010000₂
CC0[7:0] resets to vvvvvvvv₂
(vendor-dependent reset value)
CCVALUE0[5:0] - Current calibration value field.
This field controls the amount of current drive for the even-num-
bered DQ and DQN pins.
Figure 29 : Current Calibration 1 (CC1) Register
76543210
reserved
CCVALUE1[5:0]
Current Calibration 1 Register
Read/write register
SADR[7:0]: 00010001₂
CC1[7:0] resets to vvvvvvvv₂
(vendor-dependent reset value)
CCVALUE1[5:0] - Current calibration value field.
This field controls the amount of current drive for the odd-num-
bered DQ and DQN pins.
Figure 30 : Impedance Calibration 0 (ZC0) Register
76543210
reserved
resZerCvVeAdLUE0[5:0]
Impedance Calibration 0 Register
Read/write register
SADR[7:0]: 00010010₂
ZC0[7:0] resets to 00000000₂
reserved
Figure 31 : Impedance Calibration 1 (ZC1) Register
76543210
reserved
reseZrCvVedALUE1[5:0]
Impedance Calibration 1 Register
Read/write register
SADR[7:0]: 00010011₂
ZC1[7:0] resets to 00000000₂
reserved
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Rev. 1.1 August 2006