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K4Y50164UC Datasheet, PDF (51/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)
K4Y50164UC
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XDRTM DRAM
11.0 Special Feature Description
11.1 Write Masking
Figure 50 shows the logic used by the XDR DRAM device when a write-masked command (WRM) is specified in a COLM packet. This
masking logic permits individual byte of a write data packet to be written or not written according to the value of an eight bit write mask M
[7:0].
In Figure 50, there are 16 sets of 16 bit signals forming the D1[15:0] [15:0] input bus for the Byte Mask block. These are treated as 2 x 16
8-bit bytes:
D1 [15] [15.8]
D1 [15] [7:0]
...
D1 [1] [15:8]
D1 [1] [7:0]
D1 [0] [15:8]
D1 [0] [7:0]
The eight bits of each byte is compared to the value in the byte mask field (M[7:0]). If they are not equal (NE), then the corresponding
write enable signal (WE) is asserted and the byte is written into the sense amplifier. If they are equal, then corresponding write enable
signal (WE) is deasserted and the byte is not written into the sense amplifier.
In the example of Figure 50, a WRM command performs a masked write of a 64 byte data packet to all the memory devices connected
to the RQ bus (and receiving the command). It is the job of the memory controller to search the 64 bytes to find an eight bit data value
that is not used and place it into the M [7:0] field. This will always be possible because there are 256 possible 8-bit values and there are
only 64 possible values used in the bytes in the data packet.
Figure 50 : Byte Mask Logic
S[15][15:8]
8
S[15][7:0]
WE-MSB
[15]
18
NE
WE-LSB
[15]
1
NE
8
Compare 8
Compare
88
88
M[7:0]
D1[15][15:8]
D1[15][7:0]
8
D1[15][15:8]
8
D1[15][7:0]
S[0][15:8]
WE-MSB
[0]
8
1
NE
S[0][7:0]
WE-LSB
[0]
8
1
NE
8
Compare 8
Compare
88
88
D1[0][15:8]
D1[0][7:0]
8
D1[0][15:8]
8
D1[0][7:0]
8
M[7:0]
4+3
WIDTH[2:0]
SC[3:0]
S[15:0][15:0]
16x16
16x16
Byte Mask (WR)
16x16
D1[15:0][15:0]
Width Demux (WR)
16x16
Width Mux (RD)
16x16
D[15:0][15:0]
Q[15:0][15:0]
51 of 76
4+3
WIDTH[2:0]
SC[3:0]
Rev. 1.1 August 2006