K4Y50164UC Datasheet, PDF (70/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
15.0 Package Description
15.1 Package Parasitic Summary
Table19 summarizes inductance, capacitance, and resistance values associated with each pin group for the memory component. Most
of the parameters have maximum values only, however some have both maximum and minimum values.
The first group of parameters are for the CFM/CFMN clock pair pins. They include inductance, capacitance, and resistance values.
The second group of parameters are for the RQ request pins. They include inductance, mutual inductance, capacitance, and resistance
values. There are also limits on the spread in inductance and capacitance values allowed in any one memory component.
The third group of parameters are specific to the DQ data pins and include inductance, mutual inductance, capacitance, and resistance
values. There are limits on the spread in inductance and capacitance values allowed in any one memory component.
The fourth group of parameters are for the serial interface pins. They include inductance and capacitance values.
Table 19 : Package RSL Parasitic Summary
Symbol
Parameter and Other Conditions
Minimum
Maximum
Units
L_VTERM
L_{I ,CFM}
V_TERM pin - effective input inductance per four bits
CFM/CFMN pins - effective input capaciance^b
-
2.2
nH
-
5.0
nH
C_{I ,CFM}
R_{I ,CFM}
L_{I ,RQ}
CFM/CFMN pins - effective input capaciance^b
CFM/CFMN pins - effective input resistance
RSL RQ pins - effective input inductance^b
1.8
2.4
pF
4
18
Ω
-
5.0
nH
C_{I ,RQ}
RSL RQ pins - effective input capacitance^b
1.8
2.4
pF
R_{I ,RQ}
RSL RQ pins - effective input resistance
4
18
Ω
L_12,RQ
Mutual inductance between adjacent RSL RQ signals
-
0.6
nH
∆L_I,RQ
Difference in L_I,RQ between any RSL RQ pins of a single device
-
1.8
nH
∆C_I,RQ
Difference in C_I between CFM/CFMN average and RSL RQ pins of
single device
-0.12
+0.12
pF
Z_PKG,DQ
DRSL DQ pins - package differential impednce
note - package trace length should be less than 10mm long.
70
130
Ω
C_{I ,DQ}
∆C_I,DQ
R_{I ,DQ}
L_{I ,SI}
DRSL DQ pins - effective input capacitance^a
Difference in C_I between DQi and DQNi of each DRSL pair^a
DRSL DQ pins - effective input resistance
Serial Interface effective input inductance
-
1.8
pF
-
0.06
pF
4
25
Ω
-
8.0
nH
C_{I ,SI}
Serial Interface effective input capacitance
RST, SCK, CMD
SDI,SDO
1.7
3.0
pF
-
7.0
pF
a. This is the effective die input capacitance, and does not include package capacitance.
b. CFM/RQ/SI should include package capacitance/Impedance, only DQ deos not include pacage capacitance. This value is a combina-
tion of the device I/O circuitry and package capacitance&inductance
70 of 76
Rev. 1.1 August 2006