English
Language : 

K4Y50164UC Datasheet, PDF (5/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)
◁
K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDRTM DRAM
3.0 General Description
The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions. There are three sets of pins used for normal
memory access transactions: CFM/CFMN clock pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins. The “N” appended to a
signal name denotes the complementary signal of a differential pair.
A transaction is a collection of packets needed to complete a memory access. A packet is a set of bit windows on the signals of a bus.
There are two buses that carry packets: the RQ bus and DQ bus. Each packet on the RQ bus uses a set of 2 bit-windows on each signal,
while the DQ bus uses a set of 16 bit-windows on each signal.
In the write transaction shown in Figure 1, a request packet (on the RQ bus) at clock edge T0 contains an activate (ACT) command. This
causes row Ra of bank Ba in the memory component to be loaded into the sense amp array for the bank. A second request packet at
clock edge T1 contains a write (WR) command. This causes the data packet D(a1) at edge T4 to be written to column Ca1 of the sense
amp array for bank Ba. A third request packet at clock edge T3 contains another write (WR) command. This causes the data packet
D(a2) at edge T6 to also be written to column Ca2. A final request packet at clock edge T13 contains a precharge (PRE) command.
The spacings between the request packets are constrained by the following timing parameters in the diagram: tRCD-W , tCC , and tWRP . In
addition, the spacing between the request packets and data packets is constrained by the tCWD parameter. The spacing of the CFM/
CFMN clock edges is constrained by tCYCLE.
Figure 1 : XDR DRAM Device Write and Read Transactions
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
ACT WR
a0 a1
WR
a2
DQ15..0tRCD-W
DQN15..0
tCC
tCWD
D(a1)
tWRP
D(a2)
PRE
a3
tCYCLE
Transaction a: WR a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Write Transaction
CFM
CFMN
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
RQ11..0
ACT
a0
DQ15..0
DQN15..0
tRCD-R
RD
a1
tCC
RD
a2 tRDP
tCAC
PRE
a3
Q(a1)
Q(a2)
tCYCLE
Transaction a: RD a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Read Transaction
The read transaction shows a request packet at clock edge T0 containing an ACT command. This causes row Ra of bank Ba of the mem-
ory component to load into the sense amp array for the bank. A second request packet at clock edge T5 contains a read (RD) command.
This causes the data packet Q(a1) at edge T11 to be read from column Ca1 of the sense amp array for bank Ba. A third request packet
at clock edge T7 contains another RD command. This causes the data packet Q(a2) at edge T13 to also be read from column Ca2. A final
request packet at clock edge T10 contains a PRE command.
The spacings between the request packets are constrained by the following timing parameters in the diagram: tRCD-R , tCC , and tRDP . In
addition, the spacing between the request and data packets are constrained by the tCAC parameter.
* Any system or application incorporating random access memory products should be properly designed, tested and qualified to ensure
proper use or access of such memory products. Disproportionate, excessive and/or repeated access to a particular address or
addresses may result in reduction of product life.
5 of 76
Rev. 1.1 August 2006
 ▷