K4Y50164UC Datasheet, PDF (62/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
14.0 Receive/Transmit Timing
14.1 Clocking
Figure57 shows a timing diagram for the CFM/CFMN clock pins of the memory component. This diagram represents a magnified view of
these pins. This diagram shows only one clock cycle.
CFM and CFMN are differential signals: one signal is the complement of the other. They are also high-true signals - a low voltage repre-
sents a logical zero and a high voltage represents a logical one. There are two crossing points in each clock cycle. The primary crossing
point includes the high-voltage-to-low-voltage transition of CFM (indicated with the arrowhead in the diagram). The secondary crossing
point includes the low-voltage-to-high-voltage transition of CFM. All timing events on the RSL signals are referenced to the first set of
edges.
Timing events are measured to and from the crossing point of the CFM and CFMN signals. In the timing diagram, this is how the clock-
cycle time (t_CYCLE or t_CYC, _CFM), clock-low time (t_L, _CFM) and clock-high time (t_H, _CFM) are measured.
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise (t_R, _CFM) and fall
time (t_F, _CFM) of the signals are measured from the 20% and 80% points of the full-swing levels.
20% = V_IL, CFM + 0.2*(V_IH, CFM - V_IL, CFM)
80% = V_IL, CFM + 0.8*(V_IH, CFM - V_IL, CFM)
Figure 57 : Clocking Waveforms
CFM
t_CYCLE or t_CYC,CFM
t_L,CFM
t_H,CFM
logic 1
V_IH,CFM
80%
CFMN
t_R,CFM
t_F,CFM
20%
V_IL,CFM
logic 0
62 of 76
Rev. 1.1 August 2006