K4Y50164UC Datasheet, PDF (42/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
10.0 Maintenance Operations
10.1 Refresh Transactions
Figure44 contains two timing diagrams showing examples of refresh transactions. The top timing diagram shows a single refresh opera-
tion. Bank Ba is assumed to be closed (in a precharged state) when a REFA command is received in a ROWP packet on clock edge T₀.
The REFA command causes the row addressed by the REFr register (REFH/REFM/REFL) to be opened (sensed) and placed in the
sense amp array for the bank.
Note that the REFA and REFI commands are similar to the ACT command functionally; both specify a bank address and delay value,
and both cause the selected bank to open (to become sensed.). The difference is that the ACT command is accompanied by a row
address in the ROWA packet, while the REFA and REFI commands use a row address in the REFr register (REFH/REFM/REFL).
After a time t_RAS, a ROWP packet with REFP command to bank Ba is presented. This causes the bank to be closed (precharged),
leaving the bank in the same state as when the refresh transaction began.
Note that the REFP command is equivalent to the PRE command functionally; both specify a bank address and delay value, and both
cause the selected bank to close (to become precharged).
After a time t_RP, another ROWP packet with REFA command to bank Bb is presented (banks Ba and Bb are the same in this example).
This starts a second refresh cycle. Each refresh transaction requires a total time t_RC = t_RAS + t_RP, but refresh transactions to different
banks may be interleaved like normal read and write transactions.
Note that refresh transactions always perform full-page activation, regardless of the setting in the SP1..0 field of the Configuration
register. See "Configuration (CFG) Register" on page 37. Also, see "sub-Row (Sub-Page) Sensing" on page 50.
Each row of each bank must be refreshed once in every t_REF interval. This is shown with the fourth ROWP packet with a REFA command
in the top timing diagram.
10.2 Interleaved Refresh Transaction
The lower timing diagram in Figure44 represents one way a memory controller might handle refresh maintenance in a real system.
A series of eight ROWP packets with REFA commands (except for the last which is a REFI command) are presented starting at edge T₀.
The packets are spaced with intervals of t_RR. Each REFA or REFI command is addressed to a different bank (Ba through Bh) but uses
the same row address from the REFr (REFH/REFM/REFL) register. The eighth REFI command uses this address and then increments it
so the next set of eight REFA/REFI commands will refresh the next set of rows in each bank.
A series of eight ROWP packets with REFP commands are presented effectively at edge T₁₀ (a time t_RAS after the first ROWP packet
with a REFA command). The packets are spaced with intervals of t_PP. Like the REFA/REFI commands, each REFP command is
addressed to a different bank (Ba through Bh).
This burst of eight refresh transactions fully utilizes the memory component. However, other read and write transactions may be inter-
leaved with the refresh transactions before and after the burst to prevent any loss of bus efficiency. In other words, a ROWA packet with
ACT command for a read or write could have been presented at edge T₄ (a time t_RR before the first refresh transaction starts at edge T₀).
Also, a ROWA packet with ACT command for a read or write could have been presented at edge T₃₆ (a time t_RR after the last refresh
transaction starts at edge T₃₂). In both cases, the other request packets for the interleaved read or write accesses (the precharge
commands and the read or write commands) could be slotted in among the request packets for the refresh transaction.
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Rev. 1.1 August 2006