K4Y50164UC Datasheet, PDF (27/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
8.2 Read Transactions
Figure10 shows four examples of memory read transactions. A transaction is one or more request packets (and the associated data
packets) needed to perform a memory access. The state of the memory core and the address of memory access determine how many
request packets are needed to perform the access.
The first timing diagram shows a page-hit read transaction. In this case, the selected bank is already open (a row is already present in
the sense amp array for the bank). In addition, the selected row for the memory access matches the address of the row already sensed
(a page hit). This comparison must be done in the memory controller. In this example, the access is made to row Ra of bank Ba.
In this case, read data may be directly read from the sense amp array for the bank and no row operations (actiavate or precharge) are
needed. A COL packet with RD command to column Ca1 of bank Ba is presented on edge T₀ and a second COL packet with RD
command to column Ca2 of bank Ba is presented on edge T₂. Two read data packets Q(a1) and Q(a2) follow these COL packets after
the read data delay t_CAC. The two COL packets are separated by the column-cycle time t_CC. This is also the length of each read data
packet.
The second timing diagram shows an example of a page-miss read transaction. In this case, the selected bank is already open (a row is
already present in the sense amp array for the bank). However, the selected row for the memory access does not match the address of
the row already sensed(a page miss). This comparison must be done in the memory controller. In this example, the access is made to
row Ra of bank Ba, and the bank contains a row other than Ra.
In this case, read data may not be directly read from the sense amp array for the bank. It is necessary to close the present row
(precharge) and access the requested row (activate). A precharge command (PRE to bank Ba) is presented on edge T₀. An activate
command (ACT to row Ra of bank Ba) is presented on edge T₆ a time t_RP later. A COL packet with RD command to column Ca1 of bank
Ba is presented on edge T₁₁ a time t_RCD-R later. A second COL packet with RD command to column Ca2 of bank Ba is presented on
edge T₁₃. Two read data packets Q(a1) and Q(a2) follow these COL packets after the read data delay t_CAC. The two COL packets are
separated by the column-cycle time t_CC. This is also the length of each read data packet.
The third timing diagram shows an example of a page-empty write transaction. In this case, the selected bank is already closed (no row
is present in the sense amp array for the bank). No row comparison is necessary for this case; however, the memory controller must still
remember that bank Ba has been left closed. In this example, the access is made to row Ra of bank Ba.
In this case, read data may not be directly read from the sense amp array for the bank. It is necessary to access the requested row (acti-
vated). An activate command (ACT to row Ra of bank Ba) is presented on edge T₀. A COL packet with RD command to column Ca1 of
bank Ba is presented on edge T₅ a time t_RCD-R later. A second COL packet with RD command to column Ca2 of bank Ba is presented on
edge T₇. Two read data packets Q(a1) and Q(a2) follow these COL packets after the read data delay t_CAC. The two COL packets are
separated by the column-cycle time t_CC. This is also the length of each read data packet. After the final read command, it may be neces-
sary to close the present row (precharge). A precharge command - PRE to bank Ba - is presented on edge T₁₀ a time t_RDP after the last
COL packet with a RD command. Whether the bank is closed or left open depends on the memory controller and its page policy.
The fourth timing diagram shows another example of a page-empty read transaction. This is similar to the previous example except that
it uses one read command instead of two read commands. In this case, the core parameter t_RAS may also be a constraint upon when the
precharge command may be issued.
The t_RAS measures the minimum time between an activate command and a precharge command to a bank. This time interval is also
constrained by the sum t_RCD-R + t_RDP and must be set to whichever is larger. These two constraints (t_RAS and t_RCD-R + t_RDP) will be a
function of the memory device’s speed bin and the data transfer length (the number of read commands issued between the activate and
precharge commands). In this example, the t_RAS is greater than the sum t_RCD-R + t_RDP by the amount ∆t_RDP.
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Rev. 1.1 August 2006