K4Y50164UC Datasheet, PDF (55/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
11.3 Simultaneous Activation
When the XDR DRAM supports multiple bank sets as in Figure 54, another feature may be supported, in addition to ERAW. This feature
is simultaneous activation, and the timing of several cases is shown in Figure 55.
The t_RR parameter specifies the minimum spacing between packets with activation commands in XDR DRAMs with a single bank set, or
between packets to the same bank set in a XDR DRAM with multiple bank sets. The t_RR-D parameter specifies the minimum spacing
between packets with activation commands to different bank sets in a XDR DRAM with multiple bank sets.
In Figure 55, Case 4 shows an example when both t_RR and t_RR-D must be at least 4*t_CYCLE. In such a case, activation commands to dif-
ferent bank sets satisfy the same constraint as activation commands to the same bank set.
In Figure 55, Case 2 shows an example when t_RR must be at least 4*t_CYCLE and t_RR-D must be at least 2*t_CYCLE. In such a case, an acti-
vation command to one bank set may be inserted between two activation commands to a different bank set.
In Figure 55, Case 1 shows an example when t_RR must be at least 4*t_CYCLE and t_RR-D must be at least 1*t_CYCLE. As in the previous
case, an activation command to one bank set may be inserted between two activation commands to a different bank set. In this case, the
middle activation command will not be symmetrically placed relative to the two outer activation commands.
In Figure 55, Case 0 shows an example when t_RR must be at least 4*t_CYCLE and t_RR-D must be at least 0*t_CYCLE. This means that two
activation commands may be issued on the same CFM clock edge. This is only possible by using the delay mechanism in one of the two
commands. See “Dynamic Request Scheduling” on page 23. In the example shown, the packet with the REFA command is received one
cycle before the command with the ACT command, and the REFA command includes a one cycle delay. Both activation commands will
be issued internally to different bank sets on the same CFM clock edge.
Figure 55 : Simultaneous Activation — t_RR-D Cases
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
Case 4: t_RR-D = 4*t_CYCLE
REFA & ACT have same t_RR
Case 2: t_RR-D = 2*t_CYCLE
REFA fits between two ACT
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂ T₁₃ T₁₄ T₁₅ T₁₆ T₁₇ T₁₈ T₁₉ T₂₀ T₂₁ T₂₂ T₂₃
ACT
REFA
ACT
t_RR-D
t_RR-D
ACT
REFA
t_RR-D
t_RR
ACT
t_CYCLE
note - REFA is directed to bank
set different from two ACT
Case 1: t_RR-D = 1*t_CYCLE
REFA fits between two ACT
Case 0: t_RR-D = 0*t_CYCLE
REFA simultaneous with ACT
(REFA uses delay=1*t_CYCLE)
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂ T₁₃ T₁₄ T₁₅ T₁₆ T₁₇ T₁₈ T₁₉ T₂₀ T₂₁ T₂₂ T₂₃
ACT REFA
t_RR-D
t_RR
ACT
REFA ACT
t_RR-D
note - REFA is directed to bank
set different from two ACT
t_RR
ACT
t_CYCLE
note - REFA is directed to bank
set different from ACT at T₁₂
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Rev. 1.1 August 2006