K4Y50164UC Datasheet, PDF (73/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
Table of Contents
XDR^TM DRAM
0.0 Overview ............................................................................................................................................................................................. 3
1.0 Features .............................................................................................................................................................................................. 3
2.0 Key Timing Parameters/Part Numbers ............................................................................................................................................. 4
3.0 General Description ........................................................................................................................................................................... 5
4.0 Pinouts and Definitions ..................................................................................................................................................................... 6
5.0 Pin Description ................................................................................................................................................................................. 10
6.0 Block Diagram .................................................................................................................................................................................. 11
7.0 Request Packets .............................................................................................................................................................................. 13
7.1 Request Packet Formats .............................................................................................................................................................. 13
7.2 Request Field Encoding ............................................................................................................................................................... 15
7.3 Request Packet Interactions ........................................................................................................................................................ 17
7.4 Request Interactions Cases ......................................................................................................................................................... 18
7.5 Dynamic Request Scheduling ...................................................................................................................................................... 23
8.0 Memory Operations ......................................................................................................................................................................... 25
8.1 Write Transactions ....................................................................................................................................................................... 25
8.2 Read Transactions ....................................................................................................................................................................... 27
8.3 Interleaved Transactions .............................................................................................................................................................. 29
8.4 Read/Write Interaction ................................................................................................................................................................. 31
8.5 Propagation Delay ........................................................................................................................................................................ 32
9.0 Register Operations ......................................................................................................................................................................... 34
9.1 Serial Transactions ...................................................................................................................................................................... 34
9.2 Serial Write Transactions ............................................................................................................................................................. 34
9.3 Serial Read Transactions ............................................................................................................................................................. 34
9.4 Register Summary ....................................................................................................................................................................... 36
10.0 Maintenance Operations ............................................................................................................................................................... 42
10.1 Refresh Transactions ................................................................................................................................................................ 42
10.2 Interleaved Refresh Transaction ............................................................................................................................................... 42
10.3 Calibration Transactions ........................................................................................................................................................... 44
10.4 Power State Management ......................................................................................................................................................... 45
10.5 Initialization ............................................................................................................................................................................... 47
10.6 XDR DRAM Initialization Overview ........................................................................................................................................... 48
10.7 XDR DRAM Pattern Load with WDSL Register ........................................................................................................................ 48
10.8 Sub-Row (Sub-Page) Sensing .................................................................................................................................................. 50
11.0 Special Feature Description .......................................................................................................................................................... 51
11.1 Write Masking ........................................................................................................................................................................... 51
11.2 Multiple Bank sets and the ERAW Feature ............................................................................................................................... 53
11.3 Simultaneous Activation ............................................................................................................................................................ 55
11.4 Simultaneous Precharge ........................................................................................................................................................... 56
12.0 Operating Conditions .................................................................................................................................................................... 57
12.1 Electrical Conditions .................................................................................................................................................................. 57
12.2 Timing Conditions ..................................................................................................................................................................... 58
13.0 Operating Characteristics ............................................................................................................................................................. 59
13.1 Electrical Characteristics ........................................................................................................................................................... 59
13.2 Supply Current Profile ............................................................................................................................................................... 59
13.3 Timing Characteristics ............................................................................................................................................................... 60
13.4 Timing Parameters .................................................................................................................................................................... 61
14.0 Receive/Transmit Timing ............................................................................................................................................................... 62
14.1 Clocking .................................................................................................................................................................................... 62
14.2 RSL RQ Receive Timing ........................................................................................................................................................... 63
14.3 DRSL DQ Receive Timing ........................................................................................................................................................ 64
14.4 DRSL DQ Transmit Timing ....................................................................................................................................................... 66
14.5 Serial Interface Receive Timing ................................................................................................................................................ 68
14.6 Serial Interface Transmit Timing ............................................................................................................................................... 69
15.0 Package Description ...................................................................................................................................................................... 70
15.1 Package Parasitic Summary ..................................................................................................................................................... 70
15.2 Package Dimensions (104-Ball FBGA) ..................................................................................................................................... 72
73 of 76
Rev. 1.1 August 2006