K4Y50164UC Datasheet, PDF (69/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
14.6 Serial Interface Transmit Timing
Figure62 shows a timing diagram for the serial interface pins of the memory component. This diagram represents a magnified view of the
pins and only a few clock cycles are shown.
The serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage represents a logical one.
Timing events are measured to and from the V_REF,RSL level. Because timing intervals are measured in this fashion, it is necessary to
constrain the slew rate of the signals. The rise time (t_OR,SI) and fall time (t_OF,SI) of the signals are measured from the 20% and 80%
points of the full-swing levels.
20% = V_OL,SI + 0.2*(V_OH,SI - V_OL,SI)
50% = V_OL,SI + 0.5*(V_OH,SI - V_OL,SI)
80% = V_OL,SI + 0.8*(V_OH,SI - V_OL,SI)
There is one transmit window defined for the serial interface data signal (SDO pins). This window has a maximum delay time (t_Q, _SI,MAX)
from the falling edge of the SCK clock signal and a minimum delay time (t_Q,_SI,MIN) from the next falling edge of the SCK clock signal.
When the memory component is not selected during a serial device read transaction, it will simply pass the information on the SDI input
to the SDO output. This combinational propagation delay parameter is t_P,SI. The t_CYC,SCK will need to be increased during a serial read
transaction (relative to the t_CYC,_SCK value for a serial write transaction) because of the accumulated propagation delay through all of the
XDR DRAM devices on the serial interface.
During Initialization, when the serial identification is determined, the SDI-to-SDO path is registered, so the t_CYC,SCK value can be set to
the same value as for serial write transactions. See “Initialization” on page 47.
Figure 62 : Serial Interface Transmit Waveforms
SCK
t_L,SCK
t_CYC,SCK
t_H,SCK
t_F,SCK
t_R,SCK
logic 0
V_IH,SI
80%
V_REF,RSL
20%
V_IL,SI
logic 1
SDO
SDI
t_Q,SI,MAX
t_P,SI
t_Q,SI,MIN
t_OR,SI
t_OF,SI
Combinational propagation from SDI to
SDO when the device is not selected
during a serial device read transaction.
logic 0
V_OH,SI
80%
V_REF,RSL
20%
V_OL,SI
logic 1
logic 0
V_IH,SI
80%
V_REF,RSL
20%
V_IL,SI
logic 1
69 of 76
Rev. 1.1 August 2006