K4Y50164UC Datasheet, PDF (56/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
11.4 Simultaneous Precharge
When the XDR DRAM supports multiple bank sets as in Figure54, another feature may be supported, in addition to ERAW. This feature
is simultaneous precharge, and the timing of several cases is shown in Figure56.
The t_PP parameter specifies the minimum spacing between packets with precharge commands in XDR DRAMs with a single bank set, or
between packets to the same bank set in a XDR DRAM with multiple bank sets. The t_PP-D parameter specifies the minimum spacing
between packets with precharge commands to different bank sets in a XDR DRAM with multiple bank sets.
In Figure56, Case4 shows an example when both t_PP and t_PP-D must be at least 4*t_CYCLE. In such a case, precharge commands to
different bank sets satisfy the same constraint as precharge commands to the same bank set.
In Figure56, Case2 shows an example when t_PP must be at least 4*t_CYCLE and t_PP-D must be at least 2*t_CYCLE. In such a case, a
precharge command to one bank set may be inserted between two precharge commands to a different bank set.
In Figure56, Case1 shows an example when t_PP must be at least 4*t_CYCLE and t_PP-D must be at least 1*t_CYCLE. As in the previous case,
a precharge command to one bank set may be inserted between two precharge commands to a different bank set. In this case, the
middle precharge command will not be symmetrically placed relative to the two outer precharge commands.
In Figure56, Case0 shows an example when t_PP must be at least 4*t_CYCLE and t_PP-D must be at least 0*t_CYCLE. This means that two
precharge commands may be issued on the same CFM clock edge. This is only possible by using the delay mechanism in one of the two
commnads. See “Dynamic Request Scheduling” on page 23. It is also possibly by taking advantage of the fact that two independent
precharge commands may be encoded within a single ROWP packet. In the example shown, the ROWP packet contains both a REFP
command and a PRE command. Both precharge commands will be issued internally to different bank sets on the same CFM clock edge.
Figure 56 : Simultaneous Precharge — t_PP-D Cases
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
Case 4: t_PP-D = 4*t_CYCLE
REFP & PRE have same t_RR
Case 2: t_PP-D = 2*t_CYCLE
REFP fits between two PRE
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂ T₁₃ T₁₄ T₁₅ T₁₆ T₁₇ T₁₈ T₁₉ T₂₀ T₂₁ T₂₂ T₂₃
PRE
REFP
PRE
t_PP-D
t_PP-D
PRE
REFP
t_PP-D
t_PP
PRE
t_CYCLE
note - REFP is directed to bank
set different from two PRE
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
Case 1: t_PP-D = 1*t_CYCLE
REFP fits between two PRE
Case 0: t_PP-D = 0*t_CYCLE
REFP simultaneous with PRE
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂ T₁₃ T₁₄ T₁₅ T₁₆ T₁₇ T₁₈ T₁₉ T₂₀ T₂₁ T₂₂ T₂₃
PRE REFP
t_PP-D
t_PP
PRE
PRE
REFP
t_PP-D
note - REFP is directed to bank
set different from two PRE
t_PP
PRE
t_CYCLE
note - REFP is directed to bank
set different from PRE at T₁₂
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Rev. 1.1 August 2006