K4Y50164UC Datasheet, PDF (36/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
9.4 Register Summary
Figure17 through Figure42 show the control register in the memory component. The control registers are responsible for configuring the
component’s operating mode, for managing power state transactions, for managing refresh, and for managing calibration operations.
A control register may contain up to eight bits. Each figure shows defined bits in white and reserved bits in gray. Reserved bits must be
written as 0 and must be ignored when read. Write-only fields must be ignored when read .
Each figure displays the following register information:
1. Register name
2. Register mnemonic
3. Register address (SADR [7:0] value needed to access it)
4. Read-only, write-only or read-write
5. Initialization state
6. Description of each defined register field
Figure17 shows the Serial Identification register. The register contains the SID [5:0] (serial identification field). This field contains the
serial identification value for the deice. The value is compared to the SID[5:0] field of a serial transaction to determine if the serial trans-
action is directed to this device. The serial identification value is set during the initialization sequence.
Figure18 shows the Configuration Register. It contains three fields. The first is the WIDTH field. This field allows the number of DQ/DQN
pins used for memory read and write accesses to be adjusted. The SLE field enables data to be written into the memory through the
serial interface using the WDSL register.
Figure19 shows the Power Management Register. It contains two fields. The first is the PX field. When this field is written with a “1”, the
memory component transactions from powerdown to active state. It is usually unnecessary to write a “0” into this field; this is done auto-
matically by the PDN command in a COLX packet. The PST field indicates the current power state of the memory component.
Figure20 shows the Write Data Serial Load Register. It permits data to be written into memory via the Serial Interface.
Figure23 shows the Refresh Bank Control Register. It contains two fields: BANK and MBR. The BANK field is read-write and contains
the bank address used by self-refresh during the powerdown state. The MBR field controls how many banks are refreshed during each
refresh operation. Figure24, Figure25 and Figure26 show different fields of the Refresh Row Register (high, middle and low). This read-
write field contains the row address used by self- and auto-refresh. See”Refresh Transactions” on page 42 for more details.
Figure28 and Figure29 show the Current Calibration 0 and 1 registers. They contain the CCVALUE0 and CCVALUE1 fields, respectively.
These are read-write fields which control the amount of IOL current driven by the DQ and DQN pins during a read transaction. The
Current Calibration 0 Register controls the even-numbered DQ and DQN pins, and the Current Calibration 1 controls the odd-numbered
DQ and DQN pins.
Figure30 and Figure31 show the Impedance Calibration 0 and 1 registers. They contain the ZCVALUE0 and ZCVALUE1 field, respec-
tively. These are read-write fields that control the impedance of the on-chip termination components in the DQ and DQN pins. The
Impedance Calibration 0 Register controls the even-numbered DQ and DQN pins, and the Impedance Calibration 1 controls the odd-
numbered DQ and DQN pins.
Figure 36 through Figure 41 and Figure 43 shows the test registers. This includes the TEST, DLL, PLL0, PLL1, IFT, DA and PARTn
registers. These are used during device testing. They are not to be read or written during normal operation.
Figure42 shows the DLY register. This is used to set the value of t_CAC and t_CWD used by the component. See “Timing Parameters” on
page 61.
7
6
5
reserved
Figure 17 : Serial Identification (SID) Register
4
3
2
1
0
SID[5:0]
Serial Identification Register
SADR[7:0]: 00000001₂
Read-only register
SID[7:0] resets to 00000000₂
SID[5:0] - Serial Identification field.
This field contains the serial identification value for the device.
The value is compared to the SID[5:0] field of a serial transac-
tion to determine if the serial transaction is directed to this
device. The serial identification value is set during the initializa-
tion sequence.
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Rev. 1.1 August 2006