K4Y50164UC Datasheet, PDF (34/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
9.0 Register Operations
9.1 Serial Transactions
The serial interface consists of five pins. This includes RST, SCK, CMD, SDI and SDO. SDO uses CMOS signaling levels. The other four
pins use RSL signaling levels. RST, CMD, SDI and SDO use a timing window which surrounds the falling edge of SCK. The RST pin is
used for initialization.
Figure14 and Figure15 show examples of a serial write transaction and a serial read transaction. Each transaction starts on cycle S₄ and
requires 32 SCK edges. The next serial transaction can begin on cycle S₃₆. SCK does not need to be asserted if there is no transaction.
9.2 Serial Write Transactions
The serial device write transaction in Figure14 begins with the Start [3:0] field. This consists of bits “1100” on the CMD pin. This indicates
to the XDR DRAM that the remaining 28 bits constitute a serial transaction.
The next two bits are the SCMD[1:0] field. This field contains the serial command, the bits 00 in the case of a serial device write transac-
tion.
The next eight bits are “00” and the SID[5:0] field. This field contains the serial identification of the device being accessed.
The next eight bits are the SADR[7:0] field. This field contains the serial address of the control register being accessed.
A single bit “0” follows next. This bit allows one cycle for the access time to the control register.
The next eight bits on the CMD pin is the SWD[7:0] field. this is the write data that is placed into the selected control register.
A final bit”0” is driven on the CMD pin to finish the serial write transaction.
A serial broadcast write is identical except that the contents of the SID[5:0] field in the transaction is ignored and all devices perform the
register write. The SDI and SDO pins are not used during either serial write transaction.
9.3 Serial Read Transactions
The serial device read transaction in Figure15 begins with the Start[3:0] field. This consists of bits “1100” on the CMD pin. This indicates
that the remaining 28 bits constitute a serial transaction.
The next two bits are the SCMD [1:0] field. This field contains the serial command, and the bits “10” in the case of a serial device read
transaction.
The next eight bits are “00” and the SID [5:0] field. This field contains the serial identification of the device being accessed.
The next eight bits are the SADR [7:0] field and contain the serial address of the control register being accessed.
A single bit “0” follows next. This bit allows one cycle for the access time to the control register and time to turn on the SDO output driver.
The next eight bits on the CMD pin are the sequence “00000000”. At the same time, the eight bits on the SDO pin are the SRD [7:0] field.
This is the read data that is accessed from the selected control register. Note the output timing convention here: bit SRD [7] is driven
from a time t_Q,_SI,MAX after edge S₂₆ to a time t_Q,_SI,MIN after edge S₂₇. The bit is sampled in the controller by the edge S₂₇.
A final bit “0” is driven on the CMD pin to finish the serial read transaction.
A serial forece read is identical except that the contents of the SID [5:0] field in the transaction is ignored and all devices perform the
register read. This is used for device testing.
Figure16 shows the response of a DRAM to a serial device read transaction when its internal SID [5:0] register field doesn’t match the
SID [5:0] field of the transaction. Instead of driving read data from an internal register for cycle edges S₂₇ through S₃₄ on the SDO output
pin, it passes the input data from the SDI input pin to the SDO output pin during this same period.
Table 9: SCMD Field Encoding Summary
SCMD[1:0]
00
01
10
11
Command
SDW
SBW
SDR
SFR
DESCRIPTION
Serial device write-one device is written, the one whose SID[5:0] register matches the SID[5:0]
field of the transaction.
Serial broadcast write - all devices are written, regardless of the contents of the SID [5:0] register
and the SID [5:0] transaction field.
Serial device read - one device is read, the one whose SID[5:0] register matches the SID[5:0]
field of the transaction.
Serial forced read - all devices are read, regardless of the contents of the SID[5:0] register and
the SID[5:0] transaction field
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Rev. 1.1 August 2006