K4Y50164UC Datasheet, PDF (52/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
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XDR^TM DRAM
Note that other systems might use a data transfer size that is different than the 64 bytes per t_CC interval per RQ bus that is used in the
example in Figure 50.
Figure 51 shows the timing of two successive WRM commands in COLM packets. The timing is identical to that of two successive WR
commands in COL packets. The one difference is that the COLM packet includes a M[7:0] field that indicates the reserved bit pattern (for
the eight bits of each byte) that indicates that the byte is not to be written. This requires that the alignment of bytes within the data packet
be defined, and also that the bit numbering within each byte be defined (note that this was not necessary for the unmasked WR
command). In the figure, bytes are contained within a single DQ/DQN pin pair. Thus, each pin pair carries two bytes of each data packet.
Byte[0] is transferred earlier than byte[1], and bit[0] of each byte (corresponding to M [0]) is transferred first, followed by the remaining
bits in succession).
Figure 51 : Write-Masked (WRM) Transaction Example
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂ T₁₃ T₁₄ T₁₅ T₁₆ T₁₇ T₁₈ T₁₉ T₂₀ T₂₁ T₂₂ T₂₃
WRM
a1
WRM
a2
t_CC
t_CWD
D(a1)
D(a2)
RD
a1
t_CAC
Q(a1)
t_CYCLE
Bit- and Byte-number-
ing convention for write
and read data packets.
DQ0
DQN0
Byte [0]
Byte [16+0]
[0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
DQ1
DQN1
Byte [1]
Byte [16+1]
[0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
DQ15
DQN15
Byte [15]
Byte [16+15]
[0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
52 of 76
Rev. 1.1 August 2006