K4Y50164UC Datasheet, PDF (57/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
12.0 Operating Conditions
12.1 Electrical Conditions
Table13 summarizes all electrical conditions (temperature and voltage conditions) that may be applied to the memory component. The
first section of parameters is concerned with absolute voltage, storage and operating temperatures, and the power supply, reference,
and termination voltages.
The second section of parameters determines the input voltage levels for the RSL RQ signals. The high and low voltages must satisfy a
symmetry parameter with respect to the V_{REF, RSL}.
The third section of parameters determines the input voltage levels for the RSL SI(serial interface) signals. The high and low voltages
must satisfy a symmetry parameter with respect to the V_{REF, RSL}.
The fourth section of parameters determines the input voltage levels for the CFM clock signals. The high and low voltages are specified
by a common-mode value and a swing value.
The fifth section of parameters determines the input voltage levels for the write data signals on the DRSL DQ pins. The high and low volt-
ages are specified by a common-mode value and a swing value.
Table 13 : Electrical Conditions
Symbol
Parameter
Minimum
Maximum
V_IN,ABS
V_DD,ABS
T_STORE
T_J
T_MIN
V_DD
V_REF,RSL
V_TERM,DRSL
V_IL,RQ
V_IH,RQb
R_A,RQ
V_IL,SI
V_IH,SIb
R_A,SI
V_ICM,CFM
V_ISW,CFM
V_ICM,DQ
V_ISW,DQ
Voltage applied to any pin (except V_DD) with respect to GND
Voltage on V_DD with respect to GND
- 0.3
- 0.5
Storage temperature
- 50
Junction temperature under bias during normal operation
-
Operating Temperature
0
Supply voltage applied to V_DD pins during normal operation
RSL - Reference voltage applied to V_REF pin^a
1.8 - 0.09
V_TERM,RSL
- 0.450 - 0.025
DRSL - Termination voltage applied to V_TERM pins
RSL RQ inputs -low voltage
1.2 - 0.06
V_REF,RSL - 0.45
RSL RQ inputs -high voltage
V_REF,RSL + 0.15
RSL RQ inputs - data asymmetry:
R_A,RQ = (V_IH,RQ-V_REF,RSL)/(V_REF,RSL-V_IL,RQ)
RSL Serial Interface inputs -low voltage
0.8
V_REF,RSL - 0.45
RSL Serial Interface inputs -high voltage
V_REF,RSL + 0.20
RSL Serial Interface inputs - data asymmetry:
R_A,SI = (V_IH,RQ-V_REF,RSL)/(V_REF,RSL-V_IL,RQ)
0.8
CFM/CFMN input - common mode: V_ICM,CTM = (V_IH,CFMb+V_IL,CTM)/2 ^VTERM,DRSL^-0.150
CFM/CFMN input - high-low swing: V_ISW,CFM = (V_IH,CTMb - V_IL,CTM)
0.15
DRSL DQ inputs - common mode: V_ICM,DQ = (V_IH,DQb+V_IL,DQ)/2
V_TERM,DRSL-0.150
DRSL DQ inputs - high-low swing: V_ISW,DQ = (V_IH,DQb - V_IL,DQ)
0.05
1.5
2.3
100
100
T_J,MAX
1.8 + 0.09
V_TERM,RSL
- 0.450 + 0.025
1.2 + 0.06
V_REF,RSL - 0.15
V_REF,RSL + 0.45
1.2
V_REF,RSL - 0.20
V_REF,RSL + 0.45
1.2
V_TERM,DRSL-0.075
0.30
V_TERM,DRSL-0.025
0.30
a.V_TERM,RSL is typically 1.2V±0.06V. It connects to the RSL termination components, not to this DRAM component.
b.V_IH is typically equal to V_TERM,RSL or V_TERM,DRSL (whichever is appropriate) under DC conditions in a system.
Unit
V
V
°C
°C
°C
V
V
V
V
V
V
V
V
V
V
V
V
V
57 of 76
Rev. 1.1 August 2006