K4Y50164UC Datasheet, PDF (63/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
14.2 RSL RQ Receive Timing
Figure58 shows a timing diagram for the RQ11...0 request pins of the memory component. This diagram represents a magnified view of
the pins and only a few clock cycle (CFM and CFMN are the clock signals). Timing events are measured to and from the primary CFM/
CFMN crossing point in which CFM makes its high-voltage-to-low-voltage transition. The RQ11...0 signals are low- true: a high voltage
represents a logical zero and a low voltage represents a logical one. Timing events on the RQ11... 0 pins are measured to and from the
point that the signal reaches the level of the reference voltage V_{REF, RSL.}
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise (t_R, _RQ) and fall
time (t_{F, RQ}) of the signals are measured from the 20% and 80% points of the full-swing levels.
20% = V_IL, _RQ + 0.2*(V_IH, RQ - V_IL, _RQ)
80% = V_IL, _RQ + 0.8*(V_IH, RQ - V_IL, _RQ)
There are two data receiving windows defined for each RQ11...0 signal. The first of these (labeled “0”) and a set time, t_S,_RQ, and a hold
time, t_H,_RQ, measured around the primary CFM/CFMN crossing point. The second (labeled “1”) has a set time (t_S, _RQ) and a hold time
(t_H, _RQ) measured around a point 0.5*t_CYCLE after the primary CFM/CFMN crossing point.
Figure 58 : RSL RQ Receive Waveforms
CFM
t_CYCLE
CFMN
RQ0
t_S,RQ
[1/2]•t_CYCLE
t_H,RQ
t_S,RQ
t_H,RQ
0
1
t_R,RQ
t_F,RQ
logic 0
V_IH,RQ
80%
V_REF,RSL
20%
V_IL,RQ
logic1
RQ11
t_S,RQ
[1/2]•t_CYCLE
t_H,RQ
t_S,RQ
t_H,RQ
0
1
t_R,RQ
t_F,RQ
logic 0
V_IH,RQ
80%
V_REF,RSL
20%
V_IL,RQ
logic 1
63 of 76
Rev. 1.1 August 2006