K4Y50164UC Datasheet, PDF (58/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
12.2 Timing Conditions
Table14 summarizes all timing conditions that may be applied to the memory component. The first section of parameters is concerned
with parameters for the clock signals. The second section of parameters is concerned with parameters for the request signals. The third
section of parameters is concerned with parameters is concerned with parameters for the write data signals. The fourth section of param-
eters is concerned with parameters for the serial interface signals. The fifth section is concerned with all other parameters, including
those for refresh, calibration, power state transitions, and initialization.
Table 14 : Timing Conditions
Symbol
Parameter and Other Conditions
t_CYCLE or t_CYC,CTM
CFM RSL clock - cycle time
-4000
-3200
-2400
t_R,CFM, t_F,CFM
CFM/CFMN input - rise and fall time - use minimum for test.
t_H,CFM, t_L,CFM
CFM/CFMN input - high and low times
t_R,RQ, t_F,RQ
RSL RQ input - rise/fall times (20% - 80%) - use minimum for test.
t_S,RQ, t_H,RQ
RSL RQ input to sample points (set/hold)
@ 2.50 ns > t_CYCLE ≥ 2.00 ns
@ 3.33 ns > t_CYCLE ≥ 2.50 ns
@ 3.83 ns ≥ t_CYCLE ≥ 3.33 ns
t_IR,DQ, t_IF,DQ
DRSL DQ input - rise/fall times (20% - 80%) - use minimum for test.
t_S,DQ, t_H,DQ
DRSL DQ input to sample points (set/hold)
@ 2.50 ns > t_CYCLE ≥ 2.00 ns
@ 3.33 ns > t_CYCLE ≥ 2.50 ns
@ 3.83 ns ≥ t_CYCLE ≥ 3.33 ns
t_DOFF,DQ
DRSL DQ input delay offset (fixed) to sample points
t_CYC,SCK
Serial Interface SCK input - cycle time
t_R,SCK, t_F,SCK
Serial Interface SCK input - rise and fall times
t_H,SCK, t_L,SCK
Serial Interface SCK input - high and low times
t_IR,SI, t_IF,SI
Serial Interface CMD,RST,SDI input - rise and fall times
t_S,SI,t_H,SI
Serial Interface CMD,SDI input to SCK clock edge - set/hold time
t_DLY,SI-RQ
Delay from last SCK clock edge for register write to first CFM edge with RQ
packet containing a command which uses the value in the register. Also, delay
from first CFM edge with RQ packet containing a command which modifies reg-
ister value to the first SCK clock edge for register read to this register.
t_REF
Refresh interval. Every row of every bank must be accessed at least once in this
interval with a ROW-ACT, ROWP-REF or ROWP-REFI command.
t_{REFA-REFA,AVG}
Average refresh command interval. ROWP-REFA or ROWP-REFI commands
must be issued at this average rate. This depends upon t_REF and the number of
banks and the number of rows: t_REFI = t_REF/(N_B*N_R) = t_REF/(2³*2¹¹).
N_REFA,BURST
Refresh burst limit. The number of ROWP-REFA or ROWP-REFI commands
which can be issued consecutively at the minimum command spacing.
t_BURST-REFA
Refresh burst interval. The interval between a burst of N_{REFA,BURST,MAX} ROWP-
REFA or ROWP-REFI commands and the next ROWP-REFA or ROWP-REFI
command.
t_COREINIT
Interval needed for core initialialization after power is applied.
t_CALC
Current calibration interval
Delay between packet with any command and CALC/CALZ packet
t_CMD-CALC, t_CMD-CALZ w/ PRE or REFP command
w/ any other command
t_CALCE, t_CALZE
Delay between CALC/CALZ packet and CALE packet
t_CALE-CMD
Delay between CALE packet and packet with any command
t_CMD-PDN
Last command before PDN entry
t_PDN-CFM
RSL CFM/CFMN and V_TERM stable after PDN entry
t_CFM-PDN
RSL CFM/CFMN and V_TERM stable before PDN exit
t_PDN-CMD
First command after PDN exit (includes lock time for CFM/CFMN)
Minimum
2.00
2.50
3.33
0.08
40%
0.08
0.170
0.200
0.275
0.020
0.052
0.065
0.080
-0.08
20
-
40%
-
5
10
Maximum
3.83
3.83
3.83
0.20
60%
0.26
-
-
-
0.074
-
-
-
+0.08
-
5.0
60%
5.0
-
-
-
16
t_{REFA-REFA,AVG} = 488
-
128
40
-
-
1.5
-
100
4
-
16
-
12
-
24
-
16
-
16
-
16
-
4096
-
Units
ns
ns
ns
t_CYCLE
t_CYCLE
t_CYCLE
ns
ns
ns
t_CYCLE
ns
ns
ns
t_CYCLE
ns
ns
t_CYC,SCK
ns
ns
t_CYC,SCK
ms
ns
commands
t_CYCLE
ms
ms
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
Figure(s)
Figure 57
Figure 57
Figure 57
Figure 58
Figure 58
Figure 59
Figure 59
Figure 59
Figure 61
Figure 61
Figure 61
Figure 61
Figure 61
-
Figure 44
-
-
-
-
Figure 45
Figure 45
Figure 45
Figure 45
Figure 46
Figure 46
Figure 46
Figure 46
58 of 76
Rev. 1.1 August 2006