K4Y50164UC Datasheet, PDF (33/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

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Figure 13 : Propagation Delay
XDR^TM DRAM
XDR DRAM
CFM
CFMN
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂ T₁₃ T₁₄ T₁₅ T₁₆ T₁₇ T₁₈ T₁₉ T₂₀ T₂₁ T₂₂ T₂₃
RQ11..0
DQ15..0
DQN15..0
WR
a0
t_CWD
t_∆WR
RD
b0
t_∆RW
WR
c0 _tCWD
t_CYCLE
D(a0)
t_CC
Transaction a: WR
Transaction b: RD
Transaction c: WR
t_CAC
t_{WR-BUB,XDRDRAM}
Q(b0)
D(c0)
t_CC t_{RW-BUB,XDRDRAM}
a0 = {Ba,Ca0}
b0 = {Bb,Cb0}
c0 = {Bc,Cc0}
Write-Read-Write at XDR DRAM
(portions of top and bottom timing diagrams of Figure 12 merged)
Controller _{T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23}
CFM
CFMN
WR
RD
RQ11..0
a0
t_DWR
b0
t_DRW
WR
t_CC ^c0
t_CYCLE
t_RW-BUB,XIO
DQ15..0
DQN15..0
D(a0)
t_PD-Q ^Q(b0)
D(c0)
XDR DRAM_{T-1 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22}
CFM
CFMN
RQ11..0
WR
a0
t_PD-D
t_CYCLE
RD
b0
t_{PD-RQ WR}
t_PD-D
c0 _tCWD
DQ15..0 ^tPD-RQ
DQN15..0
t_CWD
D(a0)
Transaction a: WR
Transaction b: RD
Transaction c: WR
t_PD-RQ
a0 = {Ba,Ca0}
b0 = {Bb,Cb0}
c0 = {Bc,Cc0}
t_CAC
Q(b0) _{tRW-BUB,XDRDRAM}D(c0)
t_CC
Write-Read-Write at Controller and XDR DRAM
w/ t_PD-RQ = t_PD-Q = t_PD-D = 1*t_CYCLE
t_PD-RQ
RQ
Controller
DQ
t_PD-D
t_PD-Q
RQ
XDR DRAM
DQ
33 of 76
Rev. 1.1 August 2006