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| K4Y50164UC Datasheet, PDF (26/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die) | |||
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K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDRTM DRAM
Figure 9 : Write Transactions
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
WR
WR
a1
a2
tCC
tCWD
D(a1)
D(a2)
tCYCLE
Page-hit Write Example
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
PRE
a3
ACT WR
WR
a0 a1
a2
tRP
tRCD-W tCC
D(a1)
D(a2)
tCWD
Transaction a: WR
a0 = {Ba,Ra} a1 = {Ba,Ca1}
tCYCLE
a2 = {Ba,Ca2}
a3 = {Ba}
Page-miss Write Example
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
tCWD
tDP
ACT WR
WR
PRE
RQ11..0
a0 a1
a2
tWRP
a3
DQ15..0 tRCD-W tCC
D(a1)
D(a2)
DQN15..0
tCWD
tCYCLE
Transaction a: WR
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-empty Write Example
CFM
CFMN
T0 T1 T2 T3
RQ11..0
ACT WR
a0 a1
DQ15..0 tRCD-W
DQN15..0
tCWD
T4 T5 T6 T7 T8
tRAS
tWRP
D(a1)
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
âtRAS PRE
tRP
ACT
a3
b0
tCYCLE
Bb = Ba
Transaction a: WR
Transaction b: WR
a0 = {Ba,Ra}
b0 = {Bb,Rb}
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
a3 = {Ba}
b3 = {Bb}
Page-empty Write Example - Core Limited
26 of 76
Rev. 1.1 August 2006
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