K4Y50164UC Datasheet, PDF (48/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
This continues until the last XDR DRAM device drives the SRD input of the controller. Each XDR DRAM device contains a state machine
which measures the interval t_RST-SDI,00 between the edges in which RST and SDI are both sampled zero, and uses this value to set the
SID [5:0] field of the SID (Serial Identification) register. This value allows directed read and write transactions to be made to the individual
XDR DRAM devices.
Table 10 summarizes the range of the timing parameters used for initialization by the serial interface bus.
Table 10 : Initialization Timing Parameters
Symbol
Parameter
Min Max
t_RST,10
Number of cycles between RST being sampled one and RST being sampled
zero
2
-
t_RST-SDO,11
Number of cycles between RST being sampled one and SDO being driven to
one
1
1
Number of cycles between RST being sampled zero (after being sampled one
t_RST,SDI,00 for t_RST,10,MIN or more cycles) and SDI being sampled zero. This will be equal 0
63
to the index [k] of the XDR DRAM device along the serial interface bus
Number of cycles between SDI being sampled one (after RST has been sam-
t_SDI-SDO,00 pled one for t_RST,10,MIN or more cycles and is then sampled zero) and SDO
1
1
being driven to zero
t_RST-SCK Asynchronous reset interval.
20 -
Unit Figure (s)
t_CYC,SCK
-
t_CYC,SCK
-
t_CYC,SCK
-
t_CYC,SCK
-
t_CYC,SCK
-
10.6 XDR DRAM Initialization Overview
[1] Apply voltage to VDD, VTERM, and VREF pins. VTERM and VREF voltages must be less or equal to VDD voltage at all times. Wait a
time interval t_COREINIT. Power-on reset circuit in XDR DRAM places XDR DRAM into low-power state.
[2] Assert RST, SCK, SDI and CMD to logical zero, Then:
- Pulse SCK to logical one, then to logical zero four times.
- Assert RST to logical one. Reset circuit places XDR DRAM into low-power state(identical to power-on reset)
- Perform remaining initialization sequence in Figure 48.
[3] XDR DRAM has valid Serial ID and all registers have default values that are defined in Figure17 through Figure42.
[4] Perform broadcast or directed register writes to adjust registers which need a value different from their default value.
[5] Perform Powerdown Exit sequence shown in Figure46. This includes the activity from SCK cycle S₀ through the final REFP
command.
[6] Perform termination/current calibration. The CALZ /CALE sequence shown in Figure 45 is issued 128 times. After this, each
sequence is issued once every t_CALZ or t_CALC interval.
[7] Condition the XDR DRAM banks by performing a REFA/REFI activate and REFP precharge operation to each bank eight times. This
can be interleaved to save time. The row address for the activate operation will step through eight successive values of the REFr
registers. The sequence between cycles T₀ and T₃₂ in the Interleaved Refresh Example in Figure 44 could be performed eight times
to satisfy this conditioning requirement.
10.7 XDR DRAM Pattern Load with WDSL Register
The XDR memory system requires a method of deterministically loading pattern data to XDR DRAMs before beginning Receive Timing
Calibration (RX TCAL). The method employed by the XDR DRAMs to achieve this is called Write Data Serial Load (WDSL). A WDSL
packet sends one-byte of serial data which is serially shifted into a holding register within the XDR DRAM. Initialization software sends a
sequence of WDSL packets, each of which shifts the new byte in and advances the shifter by 8 positions. In this way, XDR DRAMs of
varying widths can be loaded with a single command type.
Each sequence of WDSL packets will load one full column of data to the internal holding register of the target XDR DRAM. Depending
upon the ratio of native device width to programmed width, there may be more than one sub-column per column. After loading a full
column, a series of WR commands will be issued to sequentially transfer each sub-column of the column to the XDR DRAM core(s),
based upon the SC [3:0] bits.
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Rev. 1.1 August 2006