K4Y50164UC Datasheet, PDF (40/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
Figure 32 : Current Fuse Setting 0 (FZC0) Register
76543210
reserved
resFeZrvCeVdALUE0[5:0]
Current Fuse Setting Register
SADR[7:0]: 00010100₂
reserved
Read-only register
FZC0[7:0] resets to vvvvvvvv
(vendor-dependent reset value)
Figure 33 : Current Fuse Setting 1 (FZC1) Register
76543210
reserved
resFeZrvCeVdALUE1[5:0]
Current Fuse Setting Register
SADR[7:0]: 00010101₂
reserved
Read-only register
FZC1[7:0] resets to vvvvvvvv
(vendor-dependent reset value)
7654
VErNesDeOrvRe[d3:0]
Figure 34 : Read Only Memory 0 (ROM0) Register
3210
MASK[3:0]
Read Only Memory 0 Register
Read-only register
SADR[7:0]: 00010110₂
ROM0[7:0] resets to vvvvmmmm
MASK[3:0] - Version number of mask (0001₂ is first version).
VENDOR[3:0] - Vendor number for component:
0000 - reserved 0100-1111-reserved
0001 - Toshiba
0010 - Elpida
0011 - SEC
76
BB[1:0]
Figure 35 : Read Only Memory 1 (ROM1) Register
543
RB[2:0]
210
CB[2:0]
Read Only Memory 1 Register
Read-only register
SADR[7:0]: 00010111₂
ROM0[7:0] resets to bbrrrccc
CB[2:0] - Column address bits: #bits = 6 +CB[2:0]
RB[2:0] - Row address bits: #bits = 10 +RB[2:0]
BB[2:0] - Bank address bits: #bits = 2 +BB[2:0]
These three fields indicate how many column, row, and bank
address bits are present. An offset of {6,10,2} is added to the
field value to give the number of address bits.
Figure 36 : TEST Register
76543210
WTL WTE
reserved
TEST Register
SADR[7:0]: 00011000₂
WTE - Wire Test Enable
WTL - Wire Test Latch
Figure 37 : DLL Register
76543210
reserved
DLL Register
SADR[7:0]: 00011001₂
TBD
Read/write register
TEST[7:0] resets to 00000000₂
Read/write register
DLL[7:0] resets to 00000000₂
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Rev. 1.1 August 2006