K4Y50164UC Datasheet, PDF (21/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
Figure 6 : ACT-, RD-, WR-, PRE-to-WR Packet Interactions
CCFFMM
C^CF^FM^MN^N
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂ T₁₃ T₁₄ T₁₅ T₁₆ T₁₇ T₁₈ T₁₉ T₂₀ T₂₁ T₂₂ T₂₃
R^RQQ¹1¹1^..0..0
ACT WR
ab
DQQ1155..0..0 ^{No limit}
DDQQNN151.5.0..0
ACT WR
ab
t_RCD-W
AWd Case (activate-write different bank)
a: ROWA Packet with ACT,Ba,Ra
b: COL Packet with WR,Bb,Cb
Ba =/ Bb
AWs Case (activate-write same bank)
a: ROWA Packet with ACT,Ba,Ra
b: COL Packet with WR,Bb,Cb
Ba = Bb
CCFFMM
C^CF^FM^MN^N
R^RQQ¹1¹1^..0..0
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂ T₁₃ T₁₄ T₁₅ T₁₆ T₁₇ T₁₈ T₁₉ T₂₀ T₂₁ T₂₂ T₂₃
RD
t_∆RW
WR
a
b _tCWD
RD
t_∆RW
WR
a
b _tCWD
DQQ1155..D..00
DDQQNN151.5.0..0
t_CAC
RWd Case (read-write-different bank)
a: COL Packet with RD,Ba,Ca
b: COL Packet with WR,Bb,Cb
Q(a)
D(b)
t_CAC
t_CC t_CYCLE
RWs Case (read-write-same bank)
Ba =/ Bb
a: COL Packet with RD,Ba,Ca
b: COL Packet with WR,Bb,Cb
Q(a)
D(b)
t_CC t_CYCLE
Ba = Bb
CCFFMM
C^CF^FM^MN^N
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂ T₁₃ T₁₄ T₁₅ T₁₆ T₁₇ T₁₈ T₁₉ T₂₀ T₂₁ T₂₂ T₂₃
R^RQQ¹1¹1^..0..0
WR
WR
a _tCC b
DQQ1155..0..0
DDQQNN151.5.0..0
WR
WR
a _tCC b
WWd Case (write-write different bank)
a: COL Packet with WR,Ba,Ca
b: COL Packet with WR,Bb,Cb
Ba =/ Bb
WWs Case (write-write same bank)
a: COP Packet with WR,Ba,Ca
b: COL Packet with WR,Bb,Cb
Ba = Bb
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂ T₁₃ T₁₄ T₁₅ T₁₆ T₁₇ T₁₈ T₁₉ T₂₀ T₂₁ T₂₂ T₂₃
CCFFMM
C^CF^FM^MN^N
t_RCD-W
R^RQQ¹1¹1^..0..0
PRE WR
ab
DQQ1155..0..0 ^{No limit}
DDQQNN151.5.0..0
PRE
t_RP
ACT WR
a
t_RP+t_RCD-W ^{B b}
PWd Case (precharge-write different bank)
a: ROWP Packet with PRR,Ba
b: COL Packet with WR,Bb,Cb
Ba =/ Bb
PWs Case (precharge-write same bank)
a: ROWP Packet with PRE,Ba
b: COP Packet with WR,Bb,Cb
Ba = Bb
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Rev. 1.1 August 2006