K4Y50164UC Datasheet, PDF (4/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
2.0 Key Timing Parameters/Part Numbers
XDR^TM DRAM
Organization
Bandwidth (1/t_BIT)^a
Latency(t_RAC)^b
Bin^c
Part Number
32Mx16
64Mx8
128Mx4
256Mx2
2400
3200
4000
2400
3200
4000
2400
3200
4000
2400
3200
4000
36
A
K4Y50164UC-JCA2
35
B
K4Y50164UC-JCB3
28
C
K4Y50164UC-JCC4
36
A
K4Y50084UC-JCA2
35
B
K4Y50084UC-JCB3
28
C
K4Y50084UC-JCC4
36
A
K4Y50044UC-JCA2
35
B
K4Y50044UC-JCB3
28
C
K4Y50044UC-JCC4
36
A
K4Y50024UC-JCA2
35
B
K4Y50024UC-JCB3
28
C
K4Y50024UC-JCC4
a.Data rate measured in Mbit/s per DQ differential pair. See “Timing Conditions” on page 58 and “ Timing Characteristics” on page 60.
Note that tBIT=t_CYCLE/8
b.Read access time t_RAC (= t_RCD-R+t_CAC) measured in ns. See “Timing Parameters” on page 61.
c.Timing parameter bin. See “Timing Parameters” on page 61. This is a measure of the number of interleaved read transactions needed
for maximum efficiency (the value Ceiling(t_RC-R/t_RR-D). For bin A, t_RC-R/t_RR-D=4, and for bin B, t_RC-R/t_RR-D=5 for bin C, t_RC-R/t_RR-D =6.
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Rev. 1.1 August 2006