K4Y50164UC Datasheet, PDF (64/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
14.3 DRSL DQ Receive Timing
Figure59 shows a timing diagram for receiving write data on the DQ/DQN data pins of the memory component. This diagram represents
a magnified view of the pins and only a few clock cycles are shown (CFM and CFMN are the clock signals). Timing events are measured
to and from the primary CFM/CFMN crossing point in which CFM makes its high-voltage-to-low -voltage transition. The DQ15...0/
DQN15...0 signals are high-true: a low voltage represents a logical zero and a high voltage represents a logical one. They are also differ-
ential - timing events on the DQ15...0/DQN15... 0 pins are measured to and from the point that each differential pair crosses.
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise time (t_IR, _DQ) and
fall time (t_IF, _DQ) of the signals are measured from the 20% and 80% points of the full-swing levels.
20% = V_IL, _DQ + 0.2*(V_IH, _DQ - V_IL, _DQ)
80% = V_IL, _DQ + 0.8*(V_IH, _DQ - V_IL, _DQ)
There are 16 data receiving windows defined for each DQ15...0/DQN15... 0 pin pair. The receiving windows for a particular DQi/DQNi
pin pair is referenced to an offset parameter t_DOFF,_DQi (the index “i” may take on the values {0, 1, .. , 15} and refers to each of the DQ15...
0/DQN15... 0 pin pairs).
The t_DOFF,_DQi parameter determines the time between the primary CFM/CFMN crossing point and the offset point for the DQi/DQNi pin
pair. The 16 receiving windows are placed at times t_DOFF,_DQi + (j/8)*t_CYCLE (the index “j” may take on the values {0, 1, .. , 15} and refers
to each of the receiving windows for the DQi/DQNi pin pair).
The offset values t_DOFF,_DQi for each of the 16 DQi/DQNi pin pairs can be different. However, each is constrained to lie inside the range
{t_DOFF,_MIN, t_DOFF,_MAX}. Furthermore, each offset value t_DOFF,_DQi is static and will not change during system operation. Its value can be
determined at initialization.
The 16 receiving windows (j = 0 ... 15) for the first pair DQ0/DQN0 are labeled “0” through “15”. Each window has a set time (t_S, _DQ) and
a hold time (t_H, _DQ) measured around a point t_DOFF,_DQ0 + (j/8) *t_CYCLE after the primary CFM/CFMN crossing point.
The 16 receiving windows (j = 0 ... 15) for the each of the other pairs DQi/DQNi are also labeled “0” through “15”. Each window has a set
time (t_S, _DQ) and a hold time (t_H, _DQ) measured around a point t_DOFF,_DQi + (j/8)*t_CYCLE after the primary CFM/CFMN crossing point.
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Rev. 1.1 August 2006