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| K4Y50164UC Datasheet, PDF (19/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die) | |||
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K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDRTM DRAM
Figure 4 : ACT-, RD-, WR-, PRE-to-ACT Packet Interactions
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CCFFMM
CCFFMMN N
RRQQ111.1.0..0
ACT
a
tRR
ACT
b
ACT
a
tRAS
PRE
tRP
ACT
tRC
a
b
DDQQ115.5.0..0
DDQQNN151..50..0
AAd Case (activate-activate-different bank)
a: ROWA Packet with ACT,Ba,Ra
b: ROWA Packet with ACT,Bb,Rb
Ba =/ Bb
AAs Case (activate-activate-same bank)
a: ROWA Packet with ACT,Ba,Ra
b: ROWA Packet with ACT,Bb,Rb
Ba = Bb
CCFFMM
CCFFMMN N
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
RRQQ111.1.0..0
RD ACT
ab
DDQQ115.5.0..0 No limit
DDQQNN151..50..0
RD tRDP PRE
tRP
ACT
a
a
tRDP+tRP
b
RAd Case (read-activate-different bank)
a: COL Packet with RD,Ba,Ca
b: ROWA Packet with ACT,Bb,Rb
Ba =/ Bb
RAs Case (read-activate-same bank)
a: COL Packet with RD,Ba,Ca
b: ROWA Packet with ACT,Bb,Rb
Ba = Bb
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CCFFMM
CCFFMMNN
RRQQ1111..0..0
WR ACT
ab
WR
tWRP
PRE
tRP
ACT
a
tWRP+tRP
a
b
DDQQ1155..0..0 No limit
DDQQNN151..50..0
WAd Case (write-activate-different bank)
a: COL Packet with WR,Ba,Ca
b: ROWA Packet with ACT,Bb,Rb
Ba =/ Bb
WAs Case (write-activate-same bank)
a: COL Packet with WR,Ba,Ca
b: ROWA Packet with ACT,Bb,Rb
Ba = Bb
CCFFMM
CCFFMMN N
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
RRQQ111.1.0..0
PRE ACT
ab
DDQQ115.5.0..0 No limit
DDQQNN151..50..0
PRE
a
tRP
ACT
b
PAd Case (precharge-activate-different bank)
a: ROWP Packet with PRE,Ba
b: ROWA Packet with ACT,Bb,Rb
Ba =/ Bb
PAs Case (precharge-activate-same bank)
a: ROWP Packet with PRE,Ba
b: ROWA Packet with ACT,Bb,Rb
Ba = Bb
19 of 76
Rev. 1.1 August 2006
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