K4Y50164UC Datasheet, PDF (13/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
7.0 Request Packets
A request packet carries address and control information to the memory device. This section contains tables and diagrams for packet
formats, field encodings and packet interactions.
7.1 Request Packet Formats
There are five types of request packets:
1. ROWA — specifies an ACT command
2. COL — specifies RD and WR commands
3. COLM — specifies a WRM command
4. ROWP — specifies PRE and REF commands
5. COLX — specifies the remaining commands
Table 3 describes fields within different request packet types. Various request packet type formats are illustrated in Figure3.
Each packet type consists of 24 bits sampled on the RQ11..0 pins on two successive edges of the CFM/CFMN clock. The request packet
formats are distinguished by the OP3..0 field. This field also specifies the operation code of the desired command.
In the ROWA packet, a bank address (BA), row address (R), and command delay (DELA) are specified for the activate (ACT) command.
In the COL packet, a bank address (BC), column address (C), sub-column address (SC), command delay (DELC), and sub-opcode
(WRX) are specified for the read (RD) and write (WR) commands.
In the COLM packet, a bank address (BC), column address (C), sub-column address (SC), and mask field (M) are specified for the
masked write (WRM) command.
In the ROWP packet, two independent commands may be specified. A bank address (BP) and sub-opcode (POP) are specified for the
precharge (PRE) commands. An address field (RA) and sub-opcode (ROP) are specified for the refresh (REF) commands.
In the COLX packet, a sub-operation code field (XOP) is specified for the remaining commands.
Field
OP3..0
DELA
BA2..0
R11..0
SR1..0
WRX
DELC
BC2..0
C9..4
SC3..0
M7..0
POP2..0
BP2..0
ROP2..0
RA7..0
XOP3..0
Packet Types
ROWA/ROWP
/COL/COLM/COLX
ROWA
ROWA
ROWA
ROWA
COL
COL
COL/COLM
COL/COLM
COL/COLM
COLM
ROWP
ROWP
ROWP
ROWP
COLX
Table 3 : Request Field Description
Description
4-bit operation code that specifies packet format.
(Encoded commands are in Table 4 on page 15.)
Delay the associated row activate command by 0 or 1 t_CYCLE .
3-bit bank address for row activate command.
12-bit row address for row activate command.
2-bit sub-row address for sub-row sensing (see “Sub-Row (Sub-Page) Sensing” on page 50)
Specifies RD (=0) or WR (=1) command.
Delay the column read or write command by 0 or 1 t_CYCLE .
3-bit bank address for column read or write command.
6-bit column address for column read or write command.
4-bit subcolumn address for column read or column write command for x2/x4/x8 DQ widths.
8-bit mask for masked-write command WRM.
3-bit operation code that specifies row precharge command with a delay of 0 to 3 t_CYCLE.
(Encoded commands are in Table 6 on page 16).
3-bit bank address for row precharge command.
3-bit operation code that specifies refresh commands.
(Encoded commands are in Table 5 on page 15).
8-bit refresh address field (specifies BR bank address, delay value, and REFr load value)
4-bit extended operation code that specifies calibration and powerdown commands.
(Encoded commands are in Table 7 on page 16).
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Rev. 1.1 August 2006