HD64F3642AHV Datasheet, PDF (92/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
Bit 5Reserved bit: Bit 5 is reserved: it is always read as 0 and cannot be modified.
Bit 4SCI1 Interrupt Request Flag (IRRS1)
Bit 4: IRRS1
0
1
Description
Clearing condition:
When IRRS1 = 1, it is cleared by writing 0
Setting condition:
When an SCI1 transfer is completed
(initial value)
Bits 3 to 0Reserved Bits: Bits 3 to 0 are reserved: they are always read as 0 and cannot be
modified.
Interrupt Request Register 3 (IRR3)
Bit
Initial value
Read/Write
7
INTF7
0
R/W^*
6
INTF6
0
R/W^*
5
INTF5
0
R/W^*
4
INTF4
0
R/W^*
3
INTF3
0
R/W^*
2
INTF2
0
R/W^*
1
INTF1
0
R/W^*
0
INTF0
0
R/W^*
Note: * Only a write of 0 for flag clearing is possible.
IRR3 is an 8-bit read/write register, in which a corresponding flag is set to 1 by a transition at pin
INT₇ to INT₀. The flags are not cleared automatically when an interrupt is accepted. It is necessary
to write 0 to clear each flag. Upon reset, IRR3 is initialized to H'00.
Bits 7 to 0INT₇ to INT₀ Interrupt Request Flags (INTF7 to INTF0)
Bit n: INTFn
0
1
Description
Clearing condition:
When INTFn = 1, it is cleared by writing 0
Setting condition:
When the designated signal edge is input at pin INTn
(initial value)
(n = 7 to 0)
Rev. 6.00 Sep 12, 2006 page 70 of 526
REJ09B0326-0600