HD64F3642AHV Datasheet, PDF (337/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
Clock: Either an internal clock generated by the baud rate generator or an external clock input at
the SCK₃ pin can be selected as the SCI3 transmit/receive clock. The selection is made by means
of bit COM in SMR and bits CKE1 and CKE0 in SCR3. See table 10.12 for details on clock
source selection.
When an external clock is input at the SCK₃ pin, a clock with a frequency of 16 times the bit rate
used should be input.
When SCI3 operates on an internal clock, the clock can be output at the SCK₃ pin. In this case the
frequency of the output clock is the same as the bit rate, and the phase is such that the clock rises
at the center of each bit of transmit/receive data, as shown in figure 10.9.
Clock
Serial
data
0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 character (1 frame)
Figure 10.9 Phase Relationship between Output Clock and Transfer Data
(Asynchronous Mode) (8-Bit Data, Parity, 2 Stop Bits)
Data Transfer Operations
SCI3 Initialization: Before data is transferred on SCI3, bits TE and RE in SCR3 must first be
cleared to 0, and then SCI3 must be initialized as follows.
Note: If the operation mode or data transfer format is changed, bits TE and RE must first be
cleared to 0.
When bit TE is cleared to 0, bit TDRE is set to 1.
Note that the RDRF, PER, FER, and OER flags and the contents of RDR are retained
when RE is cleared to 0.
When an external clock is used in asynchronous mode, the clock should not be stopped
during operation, including initialization. When an external clock is used in synchronous
mode, the clock should not be supplied during operation, including initialization.
Rev. 6.00 Sep 12, 2006 page 315 of 526
REJ09B0326-0600