HD64F3642AHV Datasheet, PDF (316/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
Transmit Data Register (TDR)
Bit
Initial value
Read/Write
7
TDR7
1
R/W
6
TDR6
1
R/W
5
TDR5
1
R/W
4
TDR4
1
R/W
3
TDR3
1
R/W
2
TDR2
1
R/W
1
TDR1
1
R/W
0
TDR0
1
R/W
TDR is an 8-bit register that stores transmit data. When TSR is found to be empty, the transmit
data written in TDR is transferred to TSR, and serial data transmission is started. Continuous
transmission is possible by writing the next transmit data to TDR during TSR serial data
transmission.
TDR can be read or written by the CPU at any time.
TDR is initialized to H'FF upon reset, and in standby, watch, subactive, or subsleep mode.
Serial Mode Register (SMR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
COM CHR
PE
PM
STOP
MP
CKS1 CKS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for
the baud rate generator.
SMR can be read or written by the CPU at any time.
SMR is initialized to H'00 upon reset, and in standby, watch, subactive, or subsleep mode.
Bit 7Communication Mode (COM): Bit 7 selects whether SCI3 operates in asynchronous
mode or synchronous mode.
Bit 7: COM
0
1
Description
Asynchronous mode
Synchronous mode
(initial value)
Rev. 6.00 Sep 12, 2006 page 294 of 526
REJ09B0326-0600