HD64F3642AHV Datasheet, PDF (85/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

3.3.2 Interrupt Control Registers
Table 3.3 lists the registers that control interrupts.
Table 3.3 Interrupt Control Registers
Name
Abbreviation
R/W
Interrupt edge select register 1
IEGR1
R/W
Interrupt edge select register 2
IEGR2
R/W
Interrupt enable register 1
IENR1
R/W
Interrupt enable register 2
IENR2
R/W
Interrupt enable register 3
Interrupt request register 1
Interrupt request register 2
Interrupt request register 3
IENR3
IRR1
IRR2
IRR3
R/W
R/W^*
R/W^*
R/W^*
Note: * Write is enabled only for writing of 0 to clear a flag.
Section 3 Exception Handling
Initial Value
H'70
H'00
H'10
H'00
H'00
H'10
H'00
H'00
Address
H'FFF2
H'FFF3
H'FFF4
H'FFF5
H'FFF6
H'FFF7
H'FFF8
H'FFF9
Interrupt Edge Select Register 1 (IEGR1)
Bit
Initial value
Read/Write
7
6
5



0
1
1



4
3
2
1
0

IEG3 IEG2 IEG1 IEG0
1
0
0
0
0

R/W
R/W
R/W
R/W
IEGR1 is an 8-bit read/write register used to designate whether pins IRQ₃ to IRQ₀ are set to rising
edge sensing or falling edge sensing. Upon reset, IEGR1 is initialized to H'70.
Bit 7Reserved Bit: Bit 7 is reserved: it is always read as 0 and cannot be modified.
Bits 6 to 4Reserved Bits: Bits 6 to 4 are reserved; they are always read as 1, and cannot be
modified.
Bit 3IRQ₃ Edge Select (IEG3): Bit 3 selects the input sensing of pin IRQ₃.
Bit 3: IEG3
0
1
Description
Falling edge of IRQ3 pin input is detected
Rising edge of IRQ3 pin input is detected
(initial value)
Rev. 6.00 Sep 12, 2006 page 63 of 526
REJ09B0326-0600