HD64F3642AHV Datasheet, PDF (318/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
Bit 3Stop Bit Length (STOP): Bit 3 selects 1 bit or 2 bits as the stop bit length is asynchronous
mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is
selected the STOP bit setting is invalid since stop bits are not added.
Bit 3: STOP
Description
0
1 stop bit^*1
1
2 stop bits^*2
(initial value)
Notes: 1. In transmission, a single 1 bit (stop bit) is added at the end of a transmit character.
2. In transmission, two 1 bits (stop bits) are added at the end of a transmit character.
In reception, only the first of the received stop bits is checked, irrespective of the STOP bit setting.
If the second stop bit is 1 it is treated as a stop bit, but if 0, it is treated as the start bit of the next
transmit character.
Bit 2Multiprocessor Mode (MP): Bit 2 enables or disables the multiprocessor communication
function. When the multiprocessor communication function is enabled, the parity settings in the
PE and PM bits are invalid. The MP bit setting is only valid in asynchronous mode. When
synchronous mode is selected the MP bit should be set to 0. For details on the multiprocessor
communication function, see section 10.3.6, Multiprocessor Communication Function.
Bit 2: MP
0
1
Description
Multiprocessor communication function disabled
Multiprocessor communication function enabled
(initial value)
Bits 1 and 0Clock Select 1, 0 (CKS1, CKS0): Bits 1 and 0 choose φ/64, φ/16, φ/4, or φ as the
clock source for the baud rate generator.
For the relation between the clock source, bit rate register setting, and baud rate, see Bit Rate
Register (BRR).
Bit 1: CKS1
0
1
Bit 0: CKS0
0
1
0
1
Description
φ clock
φ/4 clock
φ/16 clock
φ/64 clock
(initial value)
Rev. 6.00 Sep 12, 2006 page 296 of 526
REJ09B0326-0600