HD64F3642AHV Datasheet, PDF (9/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Main Revisions in This Edition
Item
Page Revision (See Manual for Details)
All
—
• Notification of change in company name amended
(Before) Hitachi, Ltd. → (After) Renesas Technology Corp.
• Product naming convention amended
(Before) H8/3644 Series → (After) H8/3644 Group
(Before) H8/3644R Series → (After) H8/3644R Group
3.3.2 Interrupt Control 64
Registers
Interrupt Edge Select
Register 2 (IEGR2)
Description amended
IEGR2 is an 8-bit read/write register, used to designate whether pins INT7 to INT0, and TMIB are
set to rising edge sensing or falling edge sensing. Upon reset, IEGR2 is initialized to H'00.
Bit 7INT7 Edge Select (INTEG7): Bit 7 selects the input sensing of the INT7 pin.
Bit 7: INTEG7
0
1
Description
Falling edge of INT7 pin input is detected
Rising edge of INT7 pin input is detected
(initial value)
6.2.2 Memory Map 102, 103 Description of socket adapter deleted
Table 6.2 Socket
Adapter
Figure 6.2 Socket
Adapter Pin
Correspondence
(ZTAT)
6.8.2 Memory Map 149, 151 Description of socket adapter deleted
Table 6.14 Socket
Adapter Product
Codes
Figure 6.19 Socket
Adapter Pin
Correspondence
(F-ZTAT)
6.9 Flash Memory
165
Programming and
Erasing Precautions
Table 6.18 Flash
Memory AC
Characteristics
Table amended
Item
Symbol Min Typ Max Unit Test Conditions
Flash memory read setup time^*4 tFRS
50


µs
VCC ≥ 4.5 V
100 

VCC < 4.5 V
8.4.2 Register
182
Configuration and
Description
Port Mode Register 7
(PMR7)
Bit table amended
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
TXD
POF1
1
1
1
1
1
0
0
0





R/W

R/W
Rev. 6.00 Sep 12, 2006 page vii of xx