HD64F3642AHV Datasheet, PDF (65/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
15
87
op
0
RTE, SLEEP, NOP
15
87
op
0
rn
LDC, STC (Rn)
15
op
87
IMM
0
ANDC, ORC,
XORC, LDC (#xx:8)
Legend:
op: Operation field
rn: Register field
IMM: Immediate data
Figure 2.9 System Control Instruction Codes
2.5.8 Block Data Transfer Instruction
Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format.
Table 2.11 Block Data Transfer Instruction
Instruction
EEPMOV
Size

Function
If R4L ≠ 0 then
repeat @R5+ → @R6+
R4L – 1 → R4L
until R4L = 0
else next;
Block transfer instruction. Transfers the number of data bytes
specified by R4L from locations starting at the address indicated by
R5 to locations starting at the address indicated by R6. After the
transfer, the next instruction is executed.
Certain precautions are required in using the EEPMOV instruction. See section 2.9.3, Notes on
Use of the EEPMOV Instruction, for details.
Rev. 6.00 Sep 12, 2006 page 43 of 526
REJ09B0326-0600