HD64F3642AHV Datasheet, PDF (146/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 ROM
Notes on Use of Boot Mode:
1. When the chip (H8/3644F, H8/3643F, or H8/3642AF) comes out of reset in boot mode, it
measures the low period of the input at the SCI3’s RXD pin. The reset should end with RXD
high. After the reset ends, it takes about 100 states for the chip to get ready to measure the low
period of the RXD input.
2. In boot mode, if any data has been programmed into the flash memory (if all data is not H'FF),
all flash memory blocks are erased. Boot mode is for use when user program mode is
unavailable, such as the first time on-board programming is performed, or if the program
activated in user program mode is accidentally erased.
3. Interrupts cannot be used while the flash memory is being programmed or erased.
4. The RXD and TXD lines should be pulled up on the board.
5. Before branching to the user program (RAM address H'FBE0), the chip terminates transmit
and receive operations by its on-chip SCI3 (by clearing the RE and TE bits to 0 in the serial
control register (SCR)), but the adjusted bit rate value remains set in the bit rate register
(BRR). The transmit data output pin, TXD, goes to the high-level output state (PCR2₂ = 1 in
the port 2 control register, P2₂ = 1 in the port 2 data register).
The contents of the CPU’s internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the user program. In particular,
since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be
specified for use by the user program.
The initial values of other on-chip registers are not changed.
6. Boot mode can be entered by applying 12 V to the TEST pin and FV_PP pin in accordance with
the mode setting conditions shown in table 6.9, and then executing a reset-start. Care must be
taken with turn-on of the V_PP power supply at this time.
On reset release (a low-to-high transition), the chip determines whether 12 V is being applied
to the TEST pin and FV_PP pin, and on detecting that boot mode has been set, retains that state
internally. As the applied voltage criterion level (threshold level) at this time is the range of
approximately V_CC +2 V to 11.4 V, a transition will be made to boot mode even if a voltage
sufficient for executing programming and erasing (11.4 V to 12.6 V) is not being applied.
Therefore, when executing the boot program, the V_PP power supply must be stabilized within
the range of 11.4 V to 12.6 V before a branch is made to the RAM area, as shown in figure
6.22.
Insure that the program voltage V_PP does not exceed 12.6 V when a transition is made to boot
mode (when reset is released), and does not exceed the range 12 V ±0.6 V during boot mode
operation. If these values are exceeded, boot mode execution will not be performed correctly.
Also, do not release or cut V_PP during boot mode execution or when programming or erasing
flash memory*.
Rev. 6.00 Sep 12, 2006 page 124 of 526
REJ09B0326-0600