HD64F3642AHV Datasheet, PDF (288/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
2. Contention between FRC write and increment
If an FRC increment clock signal is generated in the T₃ state of a write cycle to the lower byte
of FRC, the write takes precedence and the counter is not incremented. Figure 9.33 shows the
timing.
FRC lower byte write cycle
T₁
T₂
T₃
φ
Address
Internal write
signal
FRC input clock
FRC address
FRC
N
M
FRC write data
Figure 9.33 Contention between FRC Write and Increment
Rev. 6.00 Sep 12, 2006 page 266 of 526
REJ09B0326-0600