HD64F3642AHV Datasheet, PDF (289/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
3. Contention between OCR write and compare match
If a compare match is generated in the T₃ state of a write cycle to the lower byte of OCRA or
OCRB, the write to OCRA or OCRB takes precedence and the compare match signal is
inhibited. Figure 9.34 shows the timing.
OCR lower byte write cycle
T₁
T₂
T₃
φ
Address
Internal write
signal
FRC
OCR address
N
N+1
OCR
N
M
Write data
Compare match
signal
Inhibited
Figure 9.34 Contention between OCR Write and Compare Match
Rev. 6.00 Sep 12, 2006 page 267 of 526
REJ09B0326-0600