HD64F3642AHV Datasheet, PDF (359/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

For further details, see section 3.3, Interrupts.
Section 10 Serial Communication Interface
10.3.8 Application Notes
The following points should be noted when using SCI3.
1. Relation between writes to TDR and bit TDRE
Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial
transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared
to 0 automatically. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1.
Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to
TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost of it has
not yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed
dependably, you should first check that bit TDRE is set to 1, then write the transmit data to
TDR once only (not two or more times).
2. Operation when a number of receive errors occur simultaneously
If a number of receive errors are detected simultaneously, the status flags in SSR will be set to
the states shown in table 10.17. If an overrun error is detected, data transfer from RSR to RDR
will not be performed, and the receive data will be lost.
Table 10.17 SSR Status Flag States and Receive Data Transfer
SSR Status Flags
Receive Data Transfer
RDRF^* OER FER PER (RSR → RDR)
Receive Error Status
1
1
0
0
×
Overrun error
0
0
1
0
O
Framing error
0
0
0
1
O
Parity error
1
1
1
0
×
Overrun error + framing error
1
1
0
1
×
Overrun error + parity error
0
0
1
1
O
Framing error + parity error
1
1
1
1
×
Overrun error + framing error + parity error
Legend:
O: Receive data is transferred from RSR to RDR.
× : Receive data is not transferred from RSR to RDR.
Note: * Bit RDRF retains its state prior to data reception.
Rev. 6.00 Sep 12, 2006 page 337 of 526
REJ09B0326-0600