HD64F3642AHV Datasheet, PDF (352/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
Sender
Communication line
Receiver A
(ID = 01)
Receiver B
(ID = 02)
Receiver C
(ID = 03)
Receiver D
(ID = 04)
Serial
data
H'01
(MPB = 1)
H'AA
(MPB = 0)
ID transmission cycle
Data transmission cycle
(specifying the receiver) (sending data to the receiver
specified buy the ID)
MPB: Multiprocessor bit
Figure 10.21 Example of Inter-Processor Communication Using Multiprocessor Format
(Sending Data H'AA to Receiver A)
There is a choice of four data transfer formats. If a multiprocessor format is specified, the parity
bit specification is invalid. See table 10.14 for details.
For details on the clock used in multiprocessor communication, see section 10.3.4, Operation in
Asynchronous Mode.
Multiprocessor Transmitting: Figure 10.22 shows an example of a flowchart for multiprocessor
data transmission. This procedure should be followed for multiprocessor data transmission after
initializing SCI3.
Rev. 6.00 Sep 12, 2006 page 330 of 526
REJ09B0326-0600