HD64F3642AHV Datasheet, PDF (353/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
Start
Read bit TDRE
1
in SSR
TDRE = 1?
No
Yes
Set bit MPBT
in SSR
Write transmit
data to TDR
2
Continue data
Yes
transmission?
No
Read bit TEND
in SSR
1. Read the serial status register (SSR)
and check that bit TDRE is set to 1,
then set bit MPBT in SSR to 0 or 1 and
write transmit data to the transmit data
register (TDR). When data is written to
TDR, bit TDRE is cleared to 0 automatically.
2. When continuing data transmission, be
sure to read TDRE = 1 to confirm that a
write can be performed before writing data
to TDR. When data is written to TDR, bit
TDRE is cleared to 0 automatically.
3. If a break is to be output when data
transmission ends, set the port PCR to 1
and clear the port PDR to 0, then clear bit
TE in SCR3 to 0.
No
TEND = 1?
Yes
3
No
Break output?
Yes
Set PDR = 0,
PCR = 1
Clear bit TE to
0 in SCR3
End
Figure 10.22 Example of Multiprocessor Data Transmission Flowchart
Rev. 6.00 Sep 12, 2006 page 331 of 526
REJ09B0326-0600