HD64F3642AHV Datasheet, PDF (137/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6.5 Flash Memory Register Descriptions
Section 6 ROM
6.5.1 Flash Memory Control Register (FLMCR)
FLMCR is an 8-bit register used for flash memory operating mode control. Transitions to program
mode, erase mode, program-verify mode, and erase-verify mode are made by setting bits in this
register. FLMCR is initialized to H'00 upon reset, in sleep mode, subsleep mode, watch mode, and
standby mode, and when 12 V is not applied to FV_PP. When 12 V is applied to FV_PP, a reset
initializes FLMCR to H'80.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
VPP



EV
PV
E
P
0
0
0
0
0
0
0
0
R



R/W^* R/W^* R/W^* R/W^*
Note: * For information on access to this register, see note 11 in section 6.9, Flash Memory
Programming and Erasing Precautions.
Bit 7Programming Power (V_PP): Bit 7 is a status flag that indicates that 12 V is applied to the
FV_PP pin. For further information, see note 5 in section 6.9, Flash Memory Programming and
Erasing Precautions.
Bit 7: VPP
0
1
Description
Clearing condition:
When 12 V is not applied to the FVPP pin
Setting condition:
When 12 V is applied to the FVPP pin
(initial value)
Bit 3Erase-Verify Mode (EV)^*: Bit 3 selects transition to or exit from erase-verify mode.
Bit 3: EV
Description
0
Exit from erase-verify mode
1
Transition to erase-verify mode
Note: * Do not set multiple bits simultaneously.
Do not release or cut the VCC or VPP power supply while a bit is set.
(initial value)
Rev. 6.00 Sep 12, 2006 page 115 of 526
REJ09B0326-0600