HD64F3642AHV Datasheet, PDF (139/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 ROM
6.5.2 Erase Block Register 1 (EBR1)
EBR1 is an 8-bit register that specifies large flash-memory blocks for programming or erasure.
EBR1 is initialized to H'F0 upon reset, in sleep mode, subsleep mode, watch mode, and standby
mode, and when 12 V is not applied to FV_PP. When a bit in EBR1 is set to 1, the corresponding
block is selected and can be programmed and erased. The erase block map is shown in figure 6.7,
and the correspondence between bits and erase blocks is shown in table 6.8.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0




LB3
LB2
LB1
LB0
1
1
1
1
0
0
0
0




R/W^* R/W^* R/W^* R/W^*
Note: * Word access cannot be used on this register; byte access must be used. For
information on access to this register, see note 11 in section 6.9, Flash Memory
Programming and Erasing Precautions. LB3 is invalid in the H8/3643F, and LB3 and
LB2 are invalid in the H8/3642AF.
Bits 7 to 4Reserved: Bits 7 to 4 are reserved; they are always read as 1, and cannot be
modified.
Bits 3 to 0Large Block 3 to 0 (LB3 to LB0): These bits select large blocks (LB3 to LB0) to be
programmed and erased.
Bits 3 to 0:
LB3 to LB0
0
1
Description
Block LB3 to LB0 is not selected
Block LB3 to LB0 is selected
(initial value)
Rev. 6.00 Sep 12, 2006 page 117 of 526
REJ09B0326-0600