HD64F3642AHV Datasheet, PDF (114/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Power-Down Modes
System Control Register 2 (SYSCR2)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0


 NESEL DTON MSON SA1
SA0
1
1
1
0
0
0
0
0



R/W
R/W
R/W
R/W
R/W
SYSCR2 is an 8-bit read/write register for power-down mode control.
Upon reset, SYSCR2 is initialized to H'E0.
Bits 7 to 5Reserved Bits: These bits are reserved; they are always read as 1, and cannot be
modified.
Bit 4Noise Elimination Sampling Frequency Select (NESEL): This bit selects the frequency
at which the watch clock signal (φ_W) generated by the subclock pulse generator is sampled, in
relation to the oscillator clock (φ_OSC) generated by the system clock pulse generator. When φ_OSC =
2 to 10 MHz, clear NESEL to 0.
Bit 4: NESEL
0
1
Description
Sampling rate is φOSC/16
Sampling rate is φOSC/4
(initial value)
Rev. 6.00 Sep 12, 2006 page 92 of 526
REJ09B0326-0600