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HD64F3642AHV Datasheet, PDF (454/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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Appendix A CPU Instruction Set
Mnemonic
Operation
Addressing Mode/
Instruction Length (Bytes)
Condition Code
JSR @@aa:8
RTS
RTE
â SPâ2 â SP
PC â @SP
PC â @aa:8
â PC â @SP
SP+2 â SP
â CCR â @SP
SP+2 â SP
PC â @SP
SP+2 â SP
I HNZVC
2 ââââââ 8
2 ââââââ 8
2
10
SLEEP
â Transit to sleep mode.
2 ââââââ 2
LDC #xx:8, CCR
LDC Rs, CCR
STC CCR, Rd
ANDC #xx:8, CCR
ORC #xx:8, CCR
XORC #xx:8, CCR
NOP
EEPMOV
B #xx:8 â CCR
B Rs8 â CCR
B CCR â Rd8
B CCRâ§#xx:8 â CCR
B CCRâ¨#xx:8 â CCR
B CCRâ#xx:8 â CCR
â PC â PC+2
â if R4Lâ 0
Repeat @R5 â @R6
R5+1 â R5
R6+1 â R6
R4Lâ1 â R4L
Until R4L=0
else next;
2
2
2
2
2
2
2
2
ââââââ 2
2
2
2
2 ââââââ 2
4 ââââââ 4
Notes: (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.
(2) If the result is zero, the previous value of the flag is retained; otherwise the flag is
cleared to 0.
(3) Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to
arithmetic operation.
(4) The number of states required for execution is 4n + 9 (n = value of R4L).
(5) Set to 1 if the divisor is negative; otherwise cleared to 0.
(6) Set to 1 if the divisor is zero; otherwise cleared to 0.
Rev. 6.00 Sep 12, 2006 page 432 of 526
REJ09B0326-0600
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