HD64F3642AHV Datasheet, PDF (343/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
If no receive error is found in the above checks, bit RDRF is set to 1, and the receive data is stored
in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the error checks identify a
receive error, bit OER, PER, or FER is set to 1 depending on the kind of error. Bit RDRF retains
its state prior to receiving the data. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
Table 10.15 shows the conditions for detecting a receive error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER, FER,
PER, and RDRF must therefore be cleared to 0 before resuming reception.
Table 10.15 Receive Error Detection Conditions and Receive Data Processing
Receive Error
Overrun error
Framing error
Parity error
Abbreviation
OER
FER
PER
Detection Conditions
When the next date receive
operation is completed while bit
RDRF is still set to 1 in SSR
When the stop bit is 0
When the parity (odd or even)
set in SMR is different from that
of the received data
Received Data Processing
Receive data is not transferred
from RSR to RDR
Receive data is transferred
from RSR to RDR
Receive data is transferred
from RSR to RDR
Figure 10.14 shows an example of the operation when receiving in asynchronous mode.
Serial
data
Start
bit
Receive
data
Parity Stop Start
bit bit bit
Receive
data
Parity Stop Mark state
bit bit (idle state)
1 0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1 0
1
1 frame
1 frame
RDRF
FER
LSI
operation
User
processing
RXI request RDRF
cleared to 0
RDR data read
0 start bit
detected
ERI request in
response to
framing error
Framing error
processing
Figure 10.14 Example of Operation when Receiving in Asynchronous Mode
(8-Bit Data, Parity, 1 Stop Bit)
Rev. 6.00 Sep 12, 2006 page 321 of 526
REJ09B0326-0600