HD64F3642AHV Datasheet, PDF (280/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
Output Compare Timing: When a compare match occurs, the output level selected by the OLVL
bit in TOCR is output at pin FTOA or FTOB. Figure 9.22 shows the output timing for output
compare A.
φ
FRC
N
N+1
N
N+1
OCRA
N
N
Compare
match A
signal
OLVLA
Clear*
FTOA
(output compare
A output pin)
Note: * By execution of a software instruction.
Figure 9.22 Output Compare A Output Timing
FRC Clear Timing: FRC can be cleared by compare match A. Figure 9.23 shows the timing.
φ
Compare
match A signal
FRC
N
H'0000
Figure 9.23 Clear Timing by Compare Match A
Rev. 6.00 Sep 12, 2006 page 258 of 526
REJ09B0326-0600