HD64F3642AHV Datasheet, PDF (320/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
Bit 5Transmit Enable (TE): Bit 5 selects enabling or disabling of the start of transmit
operation.
Bit 5: TE
Description
0
Transmit operation disabled^*1 (TXD pin is transmit data pin)^*3 (initial value)
1
Transmit operation enabled^*2 (TXD pin is transmit data pin)^*3
Notes: 1. Bit TDRE in SSR is fixed at 1.
2. When transmit data is written to TDR in this state, bit TDR in SSR is cleared to 0 and
serial data transmission is started. Be sure to carry out serial mode register (SMR)
settings to decide the transmission format before setting bit TE to 1.
3. When bit TXD in PMR7 is set to 1. When bit TXD is cleared to 0, the TXD pin functions
as an I/O port regardless of the TE bit setting.
Bit 4Receive Enable (RE): Bit 4 selects enabling or disabling of the start of receive operation.
Bit 4: RE
Description
0
Receive operation disabled^*1 (RXD pin is I/O port)
(initial value)
1
Receive operation enabled^*2 (RXD pin is receive data pin)
Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is
cleared to 0, and retain their previous state.
2. In this state, serial data reception is started when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode. Be sure to carry out serial
mode register (SMR) settings to decide the reception format before setting bit RE to 1.
Bit 3Multiprocessor Interrupt Enable (MPIE): Bit 3 selects enabling or disabling of the
multiprocessor interrupt request. The MPIE bit setting is only valid when asynchronous mode is
selected and reception is carried out with bit MP in SMR set to 1. The MPIE bit setting is invalid
when bit COM is set to 1 or bit MP is cleared to 0.
Bit 3: MPIE
Description
0
Multiprocessor interrupt request disabled (normal receive operation)
(initial value)
Clearing condition:
When data is received in which the multiprocessor bit is set to 1
1
Multiprocessor interrupt request enabled^*
Note: * Receive data transfer from RSR to RDR, receive error detection, and setting of the
RDRF, FER, and OER status flags in SSR is not performed. RXI, ERI, and setting of
the RDRF, FER, and OER flags in SSR, are disabled until data with the multiprocessor
bit set to 1 is received. When a receive character with the multiprocessor bit set to 1 is
received, bit MPBR in SSR is set to 1, bit MPIE is automatically cleared to 0, and RXI
and ERI requests (when bits TIE and RIE in serial control register (SCR) are set to 1)
and setting of the RDRF, FER, and OER flags are enabled.
Rev. 6.00 Sep 12, 2006 page 298 of 526
REJ09B0326-0600