HD64F3642AHV Datasheet, PDF (120/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Power-Down Modes
5.5.2 Clearing Subsleep Mode
Subsleep mode is cleared by an interrupt (timer A, IRQ₃ to IRQ₀, INT₇ to INT₀) or by input at the
RES pin.
• Clearing by interrupt
When an interrupt is requested, subsleep mode is cleared and interrupt exception handling
starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is
disabled in the interrupt enable register.
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see section 5.3.2, Clearing Standby
Mode.
5.6 Subactive Mode
5.6.1 Transition to Subactive Mode
Subactive mode is entered from watch mode if a timer A or IRQ₀ interrupt is requested while the
LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A,
IRQ₃ to IRQ₀, or INT₇ to INT₀ interrupt is requested. A transition to subactive mode does not take
place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable
register.
5.6.2 Clearing Subactive Mode
Subactive mode is cleared by a SLEEP instruction or by input at the RES pin.
• Clearing by SLEEP instruction
If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in
TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction
is executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep
mode is entered. Direct transfer to active mode is also possible; see section 5.8, Direct
Transfer, below.
• Clearing by RES pin
Clearing by RES pin is the same as for standby mode; see section 5.3.2, Clearing Standby
Mode.
Rev. 6.00 Sep 12, 2006 page 98 of 526
REJ09B0326-0600