HD64F3642AHV Datasheet, PDF (372/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 A/D Converter
Bits 3 to 0Channel Select (CH3 to CH0): Bits 3 to 0 select the analog input channel.
The channel selection should be made while bit ADSF is cleared to 0.
Bit 3:
CH3
0
Bit 2:
CH2
0
1
Bit 1:
CH1
*
0
1
1
0
0
1
1
0
1
Legend: * Don’t care
Bit 0:
CH0
*
0
1
0
1
0
1
0
1
0
1
0
1
Analog Input Channel
No channel selected
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Reserved
Reserved
Reserved
Reserved
(initial value)
12.2.3 A/D Start Register (ADSR)
Bit
7
6
5
4
3
2
1
0
ADSF







Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W







The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D
conversion.
A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated
edge of the external trigger signal, which also sets ADSF to 1. When conversion is complete, the
converted data is set in the A/D result register (ADRR), and at the same time ADSF is cleared
to 0.
Rev. 6.00 Sep 12, 2006 page 350 of 526
REJ09B0326-0600