HD64F3642AHV Datasheet, PDF (274/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
Timer Output Compare Control Register (TOCR)
Bit
Initial value
Read/Write
7
6
5
4



OCRS
1
1
1
0



R/W
3
OEA
0
R/W
2
OEB
0
R/W
1
OLVLA
0
R/W
0
OLVLB
0
R/W
TOCR is an 8-bit read/write register that selects the output compare output levels, enables output
compare output, and controls access to OCRA and OCRB.
TOCR is initialized to H'E0 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
Bits 7 to 5Reserved Bits: Bit 7 to 5 are reserved; they are always read as 1, and cannot be
modified.
Bit 4Output Compare Register Select (OCRS): OCRA and OCRB share the same address.
OCRS selects which register is accessed when this address is written or read. It does not affect the
operation of OCRA and OCRB.
Bit 4: OCRS
0
1
Description
OCRA is selected
OCRB is selected
(initial value)
Bit 3Output Enable A (OEA): Bit 3 enables or disables the timer output controlled by output
compare A.
Bit 3: OEA
0
1
Description
Output compare A output is disabled
Output compare A output is enabled
(initial value)
Bit 2Output Enable B (OEB): Bit 2 enables or disables the timer output controlled by output
compare B.
Bit 2: OEB
0
1
Description
Output compare B output is disabled
Output compare B output is enabled
(initial value)
Rev. 6.00 Sep 12, 2006 page 252 of 526
REJ09B0326-0600