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Section 9 Timers
Contention between TCOR Write and Compare Match: If a compare match is generated in the
T₃ state of a TCORA or TCORB write cycle, the write to TCORA or TCORB takes precedence
and the compare match signal is inhibited. Figure 9.15 shows the timing.
TCORA write cycle by CPU
T₁
T₂
T₃
φ
Address
Internal write
signal
TCNTV
TCORA address
N
N+1
TCORA
N
M
TCORA write data
Compare match
signal
Inhibited
Figure 9.15 Contention between TCORA Write and Compare Match
Rev. 6.00 Sep 12, 2006 page 234 of 526
REJ09B0326-0600